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Technologist, ASIC Development Engineering (Physical Design)

Technologist, ASIC Development Engineering (Physical Design)

Western Digital

13 - 15 years

45 - 50 Lacs

bengaluru

Posted:1 week ago| Platform:

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Skills Required

asic dft usb soc analog physical verification workflow perl pcie physical design

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Job Type

Full Time

Job Description

Position Overview:

We are looking for a highly skilled and experienced individual for SoC PD lead position for driving SoC implementation efforts from RTL to GDSII. This role is pivotal within our talented team of engineers, ensuring that we meet our GDS release timelines, PPA requirements, and all sign-off criteria for our complex semiconductor designs. This role demands a profound technical understanding of the entire implementation cycle, from start to finish, as well as exceptional leadership skills. The successful candidate will work with various functional teams and must possess a strategic vision to drive continuous improvement in our methodologies and processes.

Key Responsibilities:

To be responsible for leading RTL-to-GDSII SoC implementation effort
To collaborate with cross-functional teams, including Design, Verification, Analog, DFT, SIPI etc.
To develop and guide the team members in their work, enhancing their technical capabilities and increasing productivity.
To ensure process compliance during project execution and enable / participate in technical discussions/reviews.
To prepare and submit status reports for minimizing exposure and risks on the project or closure of escalations.
Stay abreast of industry trends and emerging technologies in related fields, and incorporate best practices into the team s workflow
Foster a culture of innovation, collaboration, and continuous improvement

Qualifications

- Bachelor s or master s degree in electrical engineering, Computer Engineering, or a related field

- A minimum of 13 to 15 years of experience in leading RTL to GDSII implementation effort across various SoCs

Proven ability in technically leading a small/medium-sized team for executing projects preferred.
Hands-on experience on the entire PD Flow from RTL to GDSII
Should have a good understanding of Floor planning, Power Planning, Placement & Optimization, CTS, Routing, Design Convergence, and Sign-off with in-depth expertise in at least one of these domains.
Working knowledge about OCV, MM/MC optimization and multi-power designs (Level shifters, Isolation cells, etc)
Exposure to static timing analysis fixes including automated ECO generation.
Strong in areas on CTS, Power, Bump planning, Floorplan
Experience with tools (e.g., Synopsys FusionCompiler, PrimeTime, Cadence Innovus, Constraints Manager, Redhawk, Calibre etc.) and methodologies.
Library preparation in any environment (Synopsys, Cadence, etc)
Working knowledge on Physical verification tasks at lower nodes (database merging / DRC / LVS / ERC / PERC / Antenna / ESD / LUP analysis/fixing) at block level/chip level
The job would require complete ownership from RTL to GDS for complete SoC
Exposure to IP Hardening for blocks like SERDES, USB PHY, PCIe, DDR will be an added advantage.
Working knowledge of scripting languages like Perl and TCL will be considered a plus
Candidate needs to be self-driven and confident in reporting the status and sharing technical results with customers.
Must have the ability to present to senior management, work in a geographically dispersed team, and be aware of cross-cultural nuances.
Should be able to define project milestones, identify risks, and call out mitigation plans.

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Technologist, ASIC Development Engineering (Physical Design)