Posted:1 day ago|
Platform:
Work from Office
Full Time
Synthesis and Timing engineer to participate in the development of large SOCs with multiple physical blocks and 300+ clock domains. He/She must be high energy candidate with strong written and verbal communication skills, technically strong to find solutions and help the team both inside and outside the organization.
REQUIRED SKILLS:RTL DesignQuality checks, mainly LintAutomation using Python and TCL5years+ experience, so not an NCG
KEY RESPONSIBILITIES:Responsible for the development of complex multi-mode / multi-corner timing constraints that are compatible for RTL and signoffDrive the effort to maintain RTL quality metrics in complex, hierarchical designs and automating that process for improved efficiency.Drive the pre-route timing checks and QoR clean up to eliminate SDC issues and ensure a quality handoff for STA checksWork with CAD on the development of pre-production synthesis (Design Compiler) and STA (Primetime) flowsRequires a mix of SDC knowledge, EDA tool competence and Tcl based scripting capability (in both EDA environment and standalone Linux Tcl shell scripts)
PREFERRED EXPERIENCE:Worked with EDA tools that enable RTL quality checksHands on experience in building the timing constraints for IPs, blocks and Full-chip implementation in both flat/hierarchical flows.Experience with analyzing the timing reports and identifying both the design and constraints related issues.Ability to multitask and grasp new flows/tools/ideasPreferred EDA tool experience: Synopsys Design Compiler/Primetime, Spyglass, Fishtail etc.
ACADEMIC CREDENTIALS:Bachelor's degree or Masters degree with 5years+ experience.
Hanker Systems (india)
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