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Synthesis and STA Engineer

5 - 10 years

45 - 65 Lacs

Hyderabad

Posted:2 months ago| Platform: Naukri logo

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Skills Required

Synthesis Static Timing Analysis Timing Constraints Timing closure DFT CPF UPF Perl Python

Work Mode

Work from Office

Job Type

Full Time

Job Description

Necessary Qualifications Bachelors or Masters degree in Electronics, Computer Science Engineering, or a related field Minimum of 5 to 7 years of experience in Implementation flows/ Synthesis and STA. Experience with Cadence, Synopsys and Mentor tools Experience with Verilog and VHDL. Experience with sign-off Static Timing Analysis, Logic equivalency checks, and Static Low Power Checks (UPF/ CPF/CLP) Formal verification for RTL 2 gates and gates2gates Conformal ECO for doing complex functional ECOs. Low power synthesis on smaller blocks and subsystems using DC/Genus Physical Aware synthesis Writing Timing Constraints sub-blocks and Top level. Flow Automation and Scripting using TCL and Python or Perl.

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