SW QA Staff Engineer

We are looking for a detail-oriented and technically strong Senior QA Engineer to join our team in validating the Radiant Place and Route Engine, with a focus on Synthesis, Mapper, and Place and Route flows. This role is essential to ensuring the correctness, performance, and robustness of our EDA toolchain used in FPGA design. You will work closely with development, validation, and product teams to define test strategies, build automated test environments, and ensure high-quality software releases.

Key Responsibilities:

Functional & Regression Testing

• Design and execute test plans for synthesis, mapping, and place-and-route flows.

• Validate logic optimization, netlist generation, constraint handling, and timing closure.

• Develop and maintain regression suites to ensure stability across software releases.

Quality of Results (QoR) Validation

• Monitor and analyze QoR metrics such as timing, area, power, and runtime.

• Identify and report regressions in synthesis and layout quality.

• Collaborate with R&D to tune algorithms and improve tool performance.

Automation & Infrastructure

• Develop automated test scripts using Python, Tcl, or shell scripting.

• Integrate test cases into CI/CD pipelines for continuous validation.

• Maintain test environments and datasets for consistent and repeatable testing.

Debugging & Issue Tracking

• Investigate test failures and tool crashes; perform root cause analysis.

• File detailed bug reports and work closely with developers to resolve issues.

• Reproduce customer-reported issues and validate fixes.

Cross-Team Collaboration

• Work with product and validation teams to align QA efforts with design goals.

• Participate in design reviews and provide feedback from a QA perspective.

• Contribute to documentation and test coverage reports.

Required Qualifications:

• Bachelor s or Master s degree in Electrical Engineering, Computer Engineering, or related field.

• 10+ years of experience in QA or validation of EDA tools, particularly in synthesis and place-and-route.

• Strong understanding of digital design flows, timing analysis, and physical design.

• Experience with scripting languages (Python, Tcl) and Linux-based environments.

• Familiarity with Verilog/VHDL, SDC constraints, and netlist formats.

• Excellent analytical, debugging, and communication skills.

Preferred Qualifications:

• Experience with Radiant Software or similar FPGA/ASIC design tools (e.g., Vivado, Quartus, Libero).

• Knowledge of FPGA architectures and device-specific optimizations.

• Experience with GUI testing and visual regression tools.

• Familiarity with version control (Git) and CI tools (Jenkins, GitLab CI).