Staff R&D Engineer - Physical Verification

Job Description

We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are an experienced and initiative-taking individual with a strong technical background in Physical design, physical verification at IP/block/full chip level implementation/methodology. You thrive in collaborative environments and possess a passion for creating innovative technology. Your expertise lies in working with advanced Finfet and GAA process challenges, and you have a proactive analytical approach with a keen eye for detail. Your dedication to delivering high-quality results is complemented by excellent communication and people skills, allowing you to effectively collaborate with both internal teams and external customers. Driven by a desire to innovate, you are eager to contribute to the success of our cutting-edge technology products. What Youll Be Doing: * Conceptualizing, designing, and productizing state-of-the-art RTL to GDS implementation for SLM monitors realized through ASIC design flow. * Designing on-chip Process, Voltage, Temperature, glitch, and Droop monitors for monitoring silicon biometrics. * Physical verification, DRC, LVS, PERC, ERC, ESD, EM and Antenna cleaning. *Co-work with Place & Route team to resolve full chip/IP/block level layout integration issues to drive Physical Verification *Coordinates with internal IP owners on IP related issues. *Coordinates with Manufacturing Team on DRC related issues. * Creating new flows/methodologies and updating existing ones through collaboration with architects and circuit design engineering teams. The Impact You Will Have: * Accelerating the integration of next-generation intelligent in-chip sensors and analytics into technology products. * Optimizing performance, power, area, schedule, and yield of semiconductor lifecycle stages. * Enhancing the reliability and differentiation of products in the market with reduced risk. * Driving innovation in Physical verification and signoff design methodologies and tools. * Contributing to the development of industry-leading SLM monitors and silicon biometrics solutions. * Collaborating with cross-functional teams to ensure the successful deployment of advanced technologies. What You’ll Need: BS/B.Tech or MS/M.Tech degree in Electrical Engineering with 5+ years of relevant industry experience. Strong Physical verification and signoff experience. Experience in DRC, LVS, DFM, ANT, ERC, ESD, EM and PERC cleaning is mandatory. Proficiency with Digital design tool from any EDA vendor, preferably from Synopsys tools like FC & ICV Sound understanding of Physical design, Physical verification and signoff concepts. Work with various implementation team to drive full-chip/block level/IP level Physical Verification Sign-off closure in (DRC, LVS, ANT, ERC, ESD, PERC, EM) for tape-out. Experience with design methodologies like developing custom scripts and enhancing flows for better execution. Experience in scripting with TCL/PERL is required. Proven track record of successful physical verification closure & tape-outs in advanced nodes (14nm, 10nm, 7nm, 5nm,3nm,2nm etc...) Exposure to Floorplan & PnR flows and tools such as ICC2/FC/Innovus are added advantage. Good understanding of reliability physics including EM, ESD, crosstalk, shielding, latchup and deep sun-micron challenges. Who You Are: * Proactive and detail-oriented with excellent problem-solving skills. * Adept at working independently and providing physical verification and signoff solutions. * Excellent communicator and team player, capable of collaborating effectively with diverse teams. * Innovative thinker with a passion for technology and continuous improvement. * Committed to delivering high-quality results and achieving project goals.