The Role:
This position is an excellent opportunity for a hard-working RTL design engineer looking for a fast-paced role employing the latest hardware design and verification methodologies to develop complex and highly configurable hardware IP that sit at the heart of Arm-based Systems.
Working as the System IP team and engaging with the world s most famous technology companies, we are driving innovation into all areas that compute is possible to help us build better solutions for the billions of people using our technology worldwide. The team owns the creation of a range of popular Arm IP, like Interconnects/NoCs, MMUs and ISPs used in multiple innovative products targeting high-end networking and enterprise markets.
Our Interconnect team develops the Arm Corelink Interconnect IP. This highly scalable IP is designed for intelligently connected AMBA-compliant SoC connectivity and can be customized for multiple performance points.
Role Overview:
The candidate will work on the RTL development of a next-generation PCI Express host bridge IP for the Infrastructure line of business. They are required to have an understanding across all the elements that enable a products successful delivery. This includes low-power design techniques and the awareness of the impact of design decisions on system performance. In addition, they will also have the ability to produce designs that are area efficient, and the verification techniques that are employed to ensure high-quality innovative designs.
Responsibilities:
Involvement in micro-architecture and logic implementation using SystemVerilog RTL coding. The planning, tracking, and coordinating of individual tasks to meet high quality goals at the planned time. Working closely with the design and verification teams to share the responsibility of delivering high qualify hardware designs, including debugging functional or performance issues with the RTL using simulation and debug tools. Collaborating with other involved teams including software and 3rd party. Improving design methodology across the System IP group and wider Arm design community. Providing direction and mentoring to other junior members of your team.
Preferred Experience:
Micro-architecture experience in PCI Express Transaction Layer and strong familiarity with Data Link Layer and Physical Layer
Experience with 8+ Years
Solid understanding of topics including transaction ordering, virtualization, MMUs, cache coherence, and host bridge functions
History of high quality, low power, high performance complex micro-architecture and RTL implementations in reasonable timescales
Experience with synthesis, static timing, and DFT
Experience with physical design methods
Knowledge of other high-speed interfaces such as AMBA CHI and/or AXI, CXL, Ethernet, DDR
Experience with scripting languages including Perl, Unix, and Makefiles
Strong communication, collaboration, and presentation skills
Education Level:
Bachelors or Master s degree or equivalent experience in Electronics and Communications Engineering/Computer Science Engineering
In return:
We offer a driven reward package including annual bonus, RSUs, healthcare and wellness support. As well as other benefits such as a supplementary pension, and 25 days annual leave (with option to buy an additional 5 days per year).
Equal Opportunities at Arm
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