Staff Engineer-Digital Design

Infineon

5 - 10 years

14 - 19 Lacs

bengaluru

Posted:None| Platform:

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Skills Required

automation asic semiconductor dft digital design soc verilog debugging perl python

Work Mode

Work from Office

Job Type

Full Time

Job Description

Candidate will be responsible for RTL design for integration of IO pads into SoC, building the required multiplexing logic and necessary power control signals integration
Job Description
In your new role you will:

Candidate will be responsible for building/maintaining highly configurable and reusable IO Subsystems (Note: An IO Subsystem is a logic IP that processes the IO Pads/IO Ring information and required logic to allow multiple on-chip peripherals to share the same IOs in a configurable manner)
Candidate will be responsible for RTL design for integration of IO pads into SoC, building the required multiplexing logic and necessary power control signals integration.
Strong fundamentals in DFT/Fault-grading and/or hands on experience.
Sound & Practical Written and Verbal Communication Skills

Your Profile
You are best equipped for this task if you have:

Must have worked in ASIC Design flow, with ASIC experience of upto 5years.
Must be strong in scripting using Perl/Python
Must be familiar with RTL design for ASIC development using Verilog.
Must be familiar with LINT (LEDA / Spyglass) , Clock-Domain-Crossing analysis, UPF, MVRC, Synthesis, Timing constraints and debugging STA reports .
Strong mindset towards automation of repetitive work.
Strong fundamentals in DFT/Fault- grading and/or hands on experience.
Sound & Practical Written and Verbal Communication Skills.
Moderate Individual Contributor with Freedom to Act, Team work and Learn

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