Sr, Staff ASIC Verification Engineer

Job Description

* Identify verification environment requirements from its various sources (Specifications, Design functionality, Interfaces, etc ) * Generate verification test plan, verification environment documentation and test environment usage documentation * Define, develop, and verify complex UVM verification environments * Evaluates and exercises various aspects of the development flow. May include such items as Verilog/SystemVerilog development, functional simulation, constraint development, test planning, behavioral modelling, and verification coverage metrics (functional coverage and code coverage) * Collaborate with architect, designers , VIP team to accomplish tasks. * Identify design problems, possible corrective actions and/or inconsistencies on documented functionality * Work with peers to improve methodologies and improve execution efficiency. * Adhere to quality standards and good test and verification practices. * Work as a lead, mentor junior engineers, and help them in debugging complex problems. * Able to Support Customer issues, by their reproduction and analysis. * Should be able multitask between different activities. Key Qualifications * Proven desire to learn and explore new state of the art technologies * Demonstrate good written and spoken English communication skills * Demonstrate good review and problem-solving skills * Knowledgeable with Verilog, VHDL and/or SystemVerilog * Knowledgeable with scripting languages (BASH/TCSH/PERL/PYTHON/TCL) is a plus * Understanding of verification methodology such as UVM . * Good organization and communication skills * Be a solution provider. * 8+ years of relevant experience