Home
Jobs

Sr./ Lead Design Verification

4 - 12 years

0 Lacs

Posted:2 weeks ago| Platform: Linkedin logo

Apply

Work Mode

On-site

Job Type

Full Time

Job Description

Experience: 4 to 12 Years. Location: Bangalore. Must have hands-on experience coding in System Verilog/UVM. Experience developing testbenches for block level or IP level verification. Experience working on subsystem or SoC level would be helpful. Candidates should be proactive in communication and be able to work independently to self-manage the deliverable as per the schedules. Developing and maintaining block level test benches. Vplan, regression and coverage closure. Work on testbenches with real number modeling. Netlist and Gate level simulations. Notice Period: 30 to 90 days Show more Show less

Mock Interview

Practice Video Interview with JobPe AI

Start Design Interview Now
ACL Digital
ACL Digital

Information Technology and Services

Palo Alto

201-500 Employees

147 Jobs

    Key People

  • Pankaj Rai

    CEO
  • Chetan Dutta

    Vice President

RecommendedJobs for You