Sr. DV Engineer

Sasken Silicon Technolgies

8 - 12 years

25 - 35 Lacs

ahmedabad bengaluru

Posted:3 weeks ago| Platform:

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Skills Required

verilog uvm methodology dv engineer

Work Mode

Work from Office

Job Type

Full Time

Job Description

Job Title: Senior Design Verification Engineer (Pre-Silicon DV)

Location:

About the Role

Senior Design Verification Engineer

Key Responsibilities

Develop and implement simulation testbenches and low-power simulation setups
Create diagnostics using Assembly/C languages, assertion checkers, and coverage monitors
Define and execute detailed test plans, debug failures, and analyze coverage metrics
Collaborate with cross-functional teams to ensure verification goals are met
Work independently or as part of a team to drive verification activities from concept to closure

Required Skills & Experience

8+ years of hands-on experience in
design verification
of IPs and SoCs
Strong foundation in
computer architecture
and
verification methodologies
Proficiency in
Verilog
,
SystemVerilog
, and
UVM
for complex testbench development
Experience with
EDA simulation tools
and
SystemVerilog assertions
Deep protocol-level expertise in:

AMBA (AXI/AHB/APB)
Bluetooth MAC
Wi-Fi 802.11 MAC layer
(Optional)
PCIe MAC
,
USB MAC
protocols

Proven experience in
Low Power Simulation
,
UPF setup
, and debugging low-power failures
Familiarity with scripting languages such as
Perl
,
Unix Shell
, or similar
Exposure to
assembly language programming
is a plus
Excellent
written and verbal communication
skills

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