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SOC Physical Design Engineer Lead : Noida

10 - 15 years

20 - 35 Lacs

Noida

Posted:3 months ago| Platform: Naukri logo

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Skills Required

Innovus PNR Floorplan Physical Design timing analysis STA ASIC Synthesis Synthesis Floor Planning Timing Closure

Work Mode

Work from Office

Job Type

Full Time

Job Description

Collaborate with the design team for the implementation of various hard IPs and the SoC top level. Lead the top-level implementation of SoC designs, including IO ring integration. Utilize Synopsys Fusion Compiler for physical and WLM synthesis. Perform timing analysis and resolve timing issues related to implementation. Conduct DFT insertion and ensure robust design for testability. Execute place and route flows using Cadence Innovus and Synopsys Fusion Compiler. Manage chip-level and block-level design implementation. Design and analyze IO rings. Implement FlipChip SoC designs, including RDL routing. Ensure timing and design signoff, including STA, LVS, and DRC. Utilize tools such as Synopsys Design Compiler, DFT Compiler, PrimeTime, Cadence Innovus, and Mentor Graphics Calibre for various implementation tasks. Interested candidates can share their resumes to shubhanshi@incise.in

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Information Technology

Silicon Valley

50-200 Employees

27 Jobs

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