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Proxelera
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SoC DV Engineer

SoC DV Engineer

4 - 10 years

|

5 - 9 Lacs

Posted:1 day ago| Platform:

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Skills Required

design verification git eda tools soc ethernet debugging perl system verilog python scripting

Work Mode

Work from Office

Job Type

Full Time

Job Description

4 to 10 years experience in SoC/Subsystem Design Verification
SystemVerilog and UVM
Testbench creation experience is a must
Own and drive
- Defining/Implementation of test plans
- Debugging complex issues
- Completion of coverage including gate-level simulations
Experience in writing SVA (SystemVerilog Assertions) is a must
Protocol Expertise (Deep knowledge and hands-on expertise) on one or more of the following
- PCIe, UCIe, CXL, or NVMe
- AXI, ACE or CHI
- Ethernet
- DDR, LPDDR or HBM
Should have worked on verification of at least three full-chip/subsystem DV projects
EDA tools Synopsys VCS/ Cadence Xcelium and Verdi debugger
Experience of Power Aware Simulations using UPF is desirable (not a must)
Expertise with at least one scripting language (Python, Perl, Tcl, etc.) is a must

Experience using one or more revision control systems like Git, Perforce, Clearcase, etc. is necessary

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