Silicon Engineer, PD

Role Overview: Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) team is responsible for powering Microsoft's Intelligent Cloud mission by delivering core infrastructure and foundational technologies for Microsoft's online businesses globally. As a Sr. Physical Design Engineer, you will play a crucial role in optimizing blocks for Power, Performance, and Area, ensuring design specifications are met, and collaborating with cross-functional teams to drive technical solutions for managing and optimizing the Cloud infrastructure. Key Responsibilities: - Own execution from synthesis to place and route of partitions through floorplanning for optimizing blocks for Power, Performance, and Area - Develop and implement robust clock distribution strategies that meet design specifications - Converge the design through all signoff aspects including timing, EMIR, physical/layout fixes, formal equivalence verification, low power verification, and all signoff checks - Own Timing analysis and convergence at Subsystem/SubChip level - Drive Hierarchical Timing ECOs at Subsystem/Subchip level and pushdown timing ECOs at top-level and block interfaces - Implement Engineering Change Orders (ECOs) for power and timing convergence - Coordinate effectively with cross-functional teams such as DFT, RTL/Design/IP, STA, CAD, Architecture, Power & Performance - Mentor junior engineers on technical issues - Provide technical leadership and foster collaboration across teams Qualifications: - BS/BE/BTech/MS/ME/MTech in Electronics or Microelectronics/VLSI, or Electrical Engineering - Min 8+ years of experience in semiconductor design - Great communication, collaboration, and teamwork skills - Proven track record in implementing designs through synthesis, floorplanning, place and route, extraction, timing, and physical verification - Expertise in timing analysis, timing ECOs strategies, and timing signoff is a must - Experience in large SoC/CPU/IP design tape-out in the latest foundry process nodes is preferred - Strong understanding of constraints generation, STA, timing optimization, and timing closure - Hands-on experience with CTS and global clock distribution methods in multi-voltage, multi-clock, multi-domain, and low power designs - Experience in power analysis, low power optimization methodology, IO/Bump planning, RDL routing, formal equivalency checks, EDA tools, and scripting capabilities This position will be open for a minimum of 5 days, with applications accepted on an ongoing basis until the position is filled.,