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2.0 - 6.0 years
7 - 11 Lacs
Hyderabad, Bengaluru
Work from Office
Position Description: STA (static timing analysis), Verilog/VHDL, and Synthesis will serve you well on our team. Showcase your deep understanding of the following physical design concepts/constraints: floor-planning, placement, congestion, and setup/hold timing closure. Embrace technical challenges with your natural passion to innovate. Ability to collaborate effectively with different functional teams and strong written/verbal communication. Ability to optimize designs for best in class in low power and high performance with logically equivalent RTL transforms. Professional experience with ECO implementation, both functional and timing closure. Familiarity with simulation, debugging tools, and working closely with DV team. Experience with multi-clock and multi-power domain designs. Familiarity with DFT insertion, and multi-mode timing constraints. Position Requirements: Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science or equivalent Experience with full-chip static timing analysis through tapeout, gate level simulations, and Functional ECO implementation with Automated flows
Posted 3 weeks ago
3 - 8 years
25 - 40 Lacs
Bengaluru
Work from Office
Job description Location: Bangalore, Hyderabad Experience: 3 to 15 years Notice Period: Immediate to 30days Job Description: • Have good knowledge of entire physical design process from floorplan till GDS generation • Good Exposure to Physical Verification Process • Have hands-on experience in latest sub-micron technologies below 10 nm • Hands on experience in leading PnR tools Synopsys ICC/ICC2 • Experience in low power designs and handling congestion or timing critical tiles will be preferred • Experience in ECO implementation preferred • Scripting skills in Perl/Tcl/Python etc
Posted 2 months ago
3 - 8 years
25 - 40 Lacs
Hyderabad
Work from Office
Job description Location: Bangalore, Hyderabad Experience: 3 to 15 years Notice Period: Immediate to 30days Job Description: • Have good knowledge of entire physical design process from floorplan till GDS generation • Good Exposure to Physical Verification Process • Have hands-on experience in latest sub-micron technologies below 10 nm • Hands on experience in leading PnR tools Synopsys ICC/ICC2 • Experience in low power designs and handling congestion or timing critical tiles will be preferred • Experience in ECO implementation preferred • Scripting skills in Perl/Tcl/Python etc
Posted 2 months ago
2 - 4 years
5 - 8 Lacs
Hyderabad
Work from Office
In this highly visible role you will be: - You will excel as you optimize designs to reach ground breaking power, area, timing goals. - Delivery of timing clean, logically equivalent netlists to physical design team. - We will empower you to collaborate with a variety of functional teams to continually question the limitations of technology. Position Description: STA (static timing analysis), Verilog/VHDL, and Synthesis will serve you well on our team. Showcase your deep understanding of the following physical design concepts/constraints: floor-planning, placement, congestion, and setup/hold timing closure. Embrace technical challenges with your natural passion to innovate. Ability to collaborate effectively with different functional teams and strong written/verbal communication. Ability to optimize designs for best in class in low power and high performance with logically equivalent RTL transforms. Professional experience with ECO implementation, both functional and timing closure. Familiarity with simulation, debugging tools, and working closely with DV team. Experience with multi-clock and multi-power domain designs. Familiarity with DFT insertion, and multi-mode timing constraints. Position Requirements: Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science or equivalent Experience with full-chip static timing analysis through tapeout, gate level simulations, and Functional ECO implementation with Automated flows
Posted 2 months ago
2 - 6 years
7 - 11 Lacs
Bengaluru, Hyderabad
Work from Office
Position Description: STA (static timing analysis), Verilog/VHDL, and Synthesis will serve you well on our team. Showcase your deep understanding of the following physical design concepts/constraints: floor-planning, placement, congestion, and setup/hold timing closure. Embrace technical challenges with your natural passion to innovate. Ability to collaborate effectively with different functional teams and strong written/verbal communication. Ability to optimize designs for best in class in low power and high performance with logically equivalent RTL transforms. Professional experience with ECO implementation, both functional and timing closure. Familiarity with simulation, debugging tools, and working closely with DV team. Experience with multi-clock and multi-power domain designs. Familiarity with DFT insertion, and multi-mode timing constraints. Position Requirements: Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science or equivalent Experience with full-chip static timing analysis through tapeout, gate level simulations, and Functional ECO implementation with Automated flows
Posted 2 months ago
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