Physical Design Engineers Mirafra Software Technologies

2.0 - 6.0 years

0 Lacs

noida, uttar pradesh

On-site

You are a Physical Design Engineer with 2-5 years of hands-on experience in different PnR steps including Floor planning, Power planning, Placement & Optimization, CTS, Routing, Static timing analysis, Post route optimization, ECO implementation, and DRC closure. You should be well versed with high frequency design & advanced tech node implementation, in-depth understanding of PG-Grid optimization, custom clock tree design, and tackling high placement density/congestion bottlenecks. Your expertise should include identifying high vs low current density paths, layer/via optimization, and Adaptive PDN experience. You must have knowledge of custom clock tree designs such as H-tree, SPINE, Multi-point CTS, Clock metrics optimization through tuning of CTS implementation. Familiarity with PnR tool knobs/recipes for PPA optimization is essential. Experience in automation using Perl/Python and tcl is required. Good communication skills are necessary as you will be working in a cross-site cross-functional team environment. The ideal candidate will have a BTECH/MTECH in Electrical/Electronics/Computer Science Engineering or an equivalent field with a minimum of 3 years of relevant experience. This is a great opportunity to be part of a fast-paced team responsible for delivering high-performance designs for high performance SoCs in sub-10nm process for the mobile space.,

Posted 1 month ago

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STA Synthesis Engineer BAY Area Technology Solutions

2.0 - 6.0 years

7 - 11 Lacs

Hyderabad, Bengaluru

Work from Office

Position Description: STA (static timing analysis), Verilog/VHDL, and Synthesis will serve you well on our team. Showcase your deep understanding of the following physical design concepts/constraints: floor-planning, placement, congestion, and setup/hold timing closure. Embrace technical challenges with your natural passion to innovate. Ability to collaborate effectively with different functional teams and strong written/verbal communication. Ability to optimize designs for best in class in low power and high performance with logically equivalent RTL transforms. Professional experience with ECO implementation, both functional and timing closure. Familiarity with simulation, debugging tools, and working closely with DV team. Experience with multi-clock and multi-power domain designs. Familiarity with DFT insertion, and multi-mode timing constraints. Position Requirements: Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science or equivalent Experience with full-chip static timing analysis through tapeout, gate level simulations, and Functional ECO implementation with Automated flows

Posted 3 months ago

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Physical Design Engineer Coventine Digital

5.0 - 10.0 years

6 - 16 Lacs

bengaluru

Work from Office

Job Description: We are seeking an experienced Physical Design Engineer with strong expertise in VCLP (Voltage-Controlled Low Power) techniques and full flow RTL to GDSII implementation. Key Responsibilities: End-to-end ownership of physical design flow from RTL to GDSII VCLP implementation and optimization (highly important) Block-level and full-chip physical design Perform timing analysis , DRC/LVS checks , and power optimization Collaborate with front-end, verification, and DFT teams for successful tape-out Must-Have Skills: Strong hands-on experience in VCLP RTL to GDSII implementation EDA tools (Cadence Innovus, Synopsys ICC2, PrimeTime, Mentor Calibre) Scripting languages: Python, TCL, Perl Deep understanding of VLSI design principles Experience with advanced nodes (7nm/5nm) Strong debugging, analytical, and communication skills Nice to Have: Exposure to low-power methodologies and constraints Familiarity with ECO flows and timing closure techniques

Posted Date not available

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