Senior Staff DDR/PCIE High Speed Interface IP Physical Design Engineer

You will be responsible for designing, optimizing, verifying, and testing electronic systems, including circuits, mechanical systems, and Digital/Analog/RF/optical systems. You will work on cutting-edge products and collaborate with cross-functional teams to meet performance requirements. Your responsibilities will include: - 12 to 16 years of experience in physical design from product-based companies. - DDRPhy /PCIE-high speed interface PD or 3DIC Expertise. - Timing Signoff experience with SNPS/CDNS tools. - PDN: IR signoff and Physical verification knowledge. - Automation skills in python/Perl/TCL. - RDL-design + Bump Spec understanding for smooth SoC PDN integration and signoff. - Proficiency in automation to drive improvements in PPA. - Experience working on multiple technology nodes in advanced processes. - Experience in low power design implementation, including Unified Power Format (UPF), multi-voltage domains, and power gating. - Familiarity with ASIC design flows and physical design methodologies. Good to Have: - Design level knowledge to optimize the implementation for PPPA. Qualcomm is an equal opportunity employer and is committed to providing reasonable accommodations for individuals with disabilities during the application/hiring process. They expect all employees to adhere to applicable policies and procedures, including security requirements for protecting confidential information. Staffing and recruiting agencies are not authorized to submit profiles, applications, or resumes for this job. For more information, you can contact Qualcomm Careers.,