3 Timing Signoff Jobs

As a highly motivated and innovative digital design engineer at Synopsys, you will play a crucial role in driving the innovations that shape the future in the Era of Pervasive Intelligence. Your expertise in ASIC design methodology and flows, particularly focusing on low power analysis and optimization, will be instrumental in empowering the creation of high-performance silicon chips and software content. With a proven track record in working with advanced nodes, especially at 5nm and below, you will be responsible for developing and driving digital design methodologies to achieve the lowest power consumption. Your strong background in both digital and physical design, coupled with your proficiency in developing timing constraints and UPF, will enable you to meet stringent power, timing, and area targets effectively. Collaborating closely with design teams and EDA tools teams, you will contribute to enhancing the power efficiency of high-performance silicon chips and driving innovation in low power design methodologies. Your role will involve conducting SAIF-based analysis, implementing best practices for low power design, and optimizing RTL designs to achieve optimal power consumption. To excel in this role, you will need to possess an MSEE or BSEE with over 20 years of digital design experience, including 15+ years of digital and/or physical design experience. Your expertise in low-power design techniques at RTL, proficiency in EDA tool flows, and excellent software and scripting skills (Perl, Tcl, Python) will be key to your success in this position. As part of the Digital Methodology Center of Excellence within Synopsys" IP team, you will collaborate with experienced engineers to develop cutting-edge digital design methodologies used across all IP development teams. Your organizational and communication skills, coupled with your ability to think and communicate at different levels of abstraction, will be essential in contributing to the successful implementation of advanced node technologies and industry-leading mixed-signal products. In addition to the challenging and rewarding work environment, Synopsys offers a comprehensive range of health, wellness, and financial benefits to cater to your needs. Your recruiter will provide more details about the salary range and benefits during the hiring process.,

Qualcomm India Private Limited is seeking a CPU Integration CAD Engineer to join the Engineering Group, specifically in the Hardware Engineering department. As part of the NUVIA team, which is now integrated into Qualcomm, you will be involved in reimagining silicon and developing computing platforms that aim to revolutionize the industry. This role offers the opportunity to collaborate with exceptionally skilled engineers to design innovative solutions that excel in performance, energy efficiency, and scalability. To qualify for this position, you must hold a Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or a related field, along with at least 6 years of experience in Hardware Engineering. Alternatively, a Master's degree with 5+ years of experience or a PhD with 4+ years of experience in a related field will also be considered. The ideal candidate will have 6 to 15 years of experience with a strong academic background. As a CPU Integration CAD Engineer at Qualcomm, you will primarily focus on enabling the floor-planning, physical design, verification, and signoff of Oryon CPU cores. Your responsibilities will include collaborating with global cross-functional teams, developing and implementing flows and methodologies for various design aspects, conducting system tests, recommending improvements, and ensuring the best power, performance, and area outcomes for the silicon products. Preferred qualifications for this role include a Bachelor's or Master's degree in Electrical/Electronics Engineering or Computer Science, extensive experience in high-performance chip development, proficiency in programming languages like Python and TCL, knowledge of data structures and algorithms, automation experience, familiarity with Physical Design tasks, expertise in advanced technology nodes, and proficiency with industry-standard tools such as Siemens/Mentor Calibre and Cadence Innovus. Qualcomm is an equal opportunity employer committed to providing reasonable accommodations for individuals with disabilities during the application and hiring process. The company expects all employees to adhere to relevant policies and procedures, including those related to security and confidentiality. Staffing and recruiting agencies are advised that only individual job seekers should utilize Qualcomm's Careers Site, as unsolicited submissions will not be accepted. For further information about this exciting opportunity, please reach out to Qualcomm Careers for more details.,

As a Hardware Engineer at Qualcomm India Private Limited, you will play a crucial role in planning, designing, optimizing, verifying, and testing electronic systems. Your responsibilities will include working on a wide range of systems such as circuits, mechanical systems, Digital/Analog/RF/optical systems, FPGA, and/or DSP systems to develop cutting-edge products. You will collaborate with cross-functional teams to ensure that the solutions meet performance requirements and contribute to the overall success of the projects. The ideal candidate for this role should possess a Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or a related field with at least 6 years of experience in Hardware Engineering. Alternatively, a Master's degree with 5+ years or a PhD with 4+ years of relevant work experience will also be considered. It is essential to have expertise in physical design, especially in DDRPhy /PCIE-high speed interface PD or 3DIC, and timing signoff experience with SNPS/CDNS tools. Proficiency in automation skills like python, Perl, or TCL is required to drive improvements in Power, Performance, and Area (PPA). The successful candidate should have a strong background in PDN, IR signoff, Physical verification knowledge, RDL-design, Bump Spec understanding, and experience working on multiple technology nodes in advanced processes. Familiarity with low power design implementation, including Unified Power Format (UPF), multi-voltage domains, and power gating is also desirable. Additionally, knowledge of ASIC design flows and physical design methodologies will be beneficial for this role. Having design-level knowledge to optimize the implementation for Power, Performance, and Area (PPA) will be considered a plus. Qualcomm believes in equal opportunities and is committed to providing accessible processes for individuals with disabilities. If you require accommodations during the application/hiring process, please reach out to Qualcomm at disability-accommodations@qualcomm.com or through the toll-free number available on their website.,