Senior SoC RTL Architect & Designer

As an RTL Design Engineer at our company, you will be responsible for owning complex SoC or large subsystem blocks end-to-end. Your tasks will include defining micro-architecture from specs, developing clean SystemVerilog/Verilog RTL, and driving integration, timing, power, and area closure with PD teams. Your involvement will be deep through design reviews, bug closure, and silicon bring-up. Key Responsibilities: - Define micro-architecture from specifications - Develop clean SystemVerilog/Verilog RTL - Drive integration, timing, power, and area closure with PD teams - Participate actively in design reviews and bug closure - Support silicon bring-up process Qualifications Required: - 8+ years of hands-on ASIC RTL experience with multiple production tapeouts - Strong micro-architecture skills - Familiarity with AMBA protocols - Experience in low-power design and clock/reset expertise - Solid exposure to DFT, synthesis constraints, ECO flows, and cross-team collaboration Additional Details: If you have experience with coherency, memory subsystems, DDR/PCIe, security blocks, SVA, or performance/power analysis, it would be considered a bonus. Please note that backgrounds limited to FPGA-only, lint/CDC-only, or management-only roles will not meet our expectations. If you are seeking a role that offers real ownership and the opportunity to make a tangible impact on silicon, this position is a perfect fit for you.,