Senior R&D Engineer, Memory Design Engineer

Develop CMOS embedded memories such as Single-Port SRAM, Dual-Port SRAM, Register Files, and ROM Design and implement memory architecture with focus on ultra-high-speed, ultra-low-power, or high-density applications Perform schematic entry, circuit simulation, layout planning, supervision, and full design verification Interface with CAD and frontend teams to automate memory compilers and generate EDA models Drive bit cell development, bit cell verification, and lead physical layout design and verification Collaborate with cross-functional teams and support integration of memory IP into advanced silicon solutions The Impact You Will Have: Advance CMOS embedded memory technologies for cutting-edge chip design Enable high-performance and energy-efficient memory IPs for diverse applications Improve memory design productivity through enhanced automation and verification flows Help integrate advanced memory into next-generation SoCs Strengthen Synopsys leadership in embedded memory solutions and silicon innovation Foster collaboration across teams to drive innovation in semiconductor memory design What You'll Need: Bachelor's or Master's degree in Electrical Engineering, Telecommunication, or a related discipline At least 5 years of hands-on experience in CMOS memory design Proficiency in schematic design, simulation, and layout of memory circuits Experience with layout parasitic extraction and layout verification/debugging tools Strong scripting skills in C-Shell and Perl; C++ or JavaScript knowledge is a plus Excellent analytical, problem-solving, and attention-to-detail skills