Senior Engineer II - Analog Design

Are you looking for a unique opportunity to be a part of something greatWant to join a 17,000-member team that works on the technology that powers the world around usLooking for an atmosphere of trust, empowerment, respect, diversity, and communicationHow about an opportunity to own a piece of a multi-billion dollar (with a B!) global organizationWe offer all that and more at Microchip Technology Inc.

People come to work at Microchip because we help design the technology that runs the world.

• Job Description

  Candidate will join the custom circuit design team to execute the design of IOs/Analog/Mixed signal circuits their integration into FPGA.

• Qualifications/Requirements

  Qualifications/Requirements

  Experience Required in Few/all of the following design areas
  

  • High Speed IO design and analysis in FPGA/SoC
  • DDR/LPDDR design and Analysis
  • Experience in General purpose IOs in different technologies
  • Good understanding of ESD and Latch up
  • Good Understanding of DDR timing and ODT functionality
  • Experience in Signal/Power integrity simulations
  • Voltage detectors, Current mirrors voltage regulators
  • Power on Reset circuits
  • Simultaneous switching Noise and Jitter simulation.

  The IO design Group Is Responsible For
  

  • Perform feasibility studies including idea creation; develop specification, design, and verification of the IOs.
  • Write IP specifications, verification plans, and documentation
  • Generate test bench and automatic regression plans
  • Responsible for simulations, verifications, help in silicon bring up and characterization of IOs
  • Candidate will be responsible for interface collaborate with and support multiple groups in organization
  • Candidate may be expected to support customer questions and help in resolving the issues

Requirements/Qualifications:

• 5-8 years of related work experience.
• Good Knowledge in Circuit design and circuit analysis
• Experience in FinFet technology.
• Good knowledge of IC chip design, development flow, process, and methodology
• Good understanding of CMOS device operation and characteristics
• Must have circuit simulation experience using Cadence, Spectre, HSPICE , or equivalent tools
• Experience in running Solido variation designer
• Experience with UNIX shell scripting or Perl scripting
• Experience with SOC tools such as mixed signal simulators and Cadence Virtuoso is required
• Excellent written and verbal communication in English
• Good analytical and problem-solving skills
• Experience in silicon validation
• Must be familiar with layout parasitic extraction tools and layout dependent impairments in advanced CMOS processes
• Must be able to work independently, create and adhere to schedules

Travel Time:

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