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Senior Engineer - DV

4 years

4 - 7 Lacs

bengaluru

Posted:4 weeks ago| Platform: GlassDoor logo

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Skills Required

design verification test ip systemverilog simulations architecture automation simulation scripting perl python tcl

Work Mode

On-site

Job Type

Part Time

Job Description

Job Requirements

Role: Senior Design Verification Engineer (VLSI)
Experience: ~4 years

Key Responsibilities:

  • Write and execute test plans for digital IP/SoC verification.
  • Develop testbenches using SystemVerilog/UVM.
  • Run simulations, debug failures, and ensure design quality.
  • Work with design and architecture teams to close verification gaps.
  • Contribute to coverage, regressions, and automation scripts.

Skills Required:

  • SystemVerilog, UVM, simulation tools (VCS/Questa/Incisive).
  • Good understanding of digital design, RTL, and verification methodology.
  • Strong debug and problem-solving skills.
  • Exposure to scripting (Perl/Python/TCL) is a plus.


Work Experience

Skills Required:

  • SystemVerilog, UVM, simulation tools (VCS/Questa/Incisive).
  • Good understanding of digital design, RTL, and verification methodology.
  • Strong debug and problem-solving skills.
  • Exposure to scripting (Perl/Python/TCL) is a plus.

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