Senior Emulation Engineer

Role

Mandatory Skills:

What you ll do:

1. Own and bring up emulation cutdowns cutdowns for

   large SoC and IP blocks

   to improve emulation performance and turnaround time.
2. Adapt and port test benches to run efficiently on hardware emulation platforms.
3. Debug and resolve issues related to

   AVIPs

   and transactors within the emulation environment.
4. Lead the bring-up and setup of

   emulation platforms (Palladium, Zebu)

   to ensure readiness for verification runs.
5. Collaborate closely with RTL designers, verification, and emulation infrastructure teams to ensure high coverage and quality.
6. Troubleshoot test failures on emulators and provide actionable feedback to design and DV teams.
7. Release validated emulation cutdowns and test benches to software, DV, or STA teams.

Who you are:

1. 6 to 10 years of experience
2. 6+ Years of experience in RTL design/verification and hardware emulation.

3. Hands-on experience with Cadence Palladium and/or Synopsys Zebu emulators.

4. Strong skills in debugging and developing AVIPs and transactors.
5. Proficiency in SystemVerilog, UVM, and scripting languages such as C, Python, Perl, and Shell.
6. Solid understanding of

   SoC architecture

   , verification methodologies, and hardware/software co-debugging.
7. Experience with waveform analysis tools (Verdi, DVE).
8. Ability to analyze, reduce, and optimize test cases while maintaining coverage and validity.
9. Excellent problem-solving and communication skills, with a collaborative mindset.