Senior Emulation and Prototyping Engineer

3 - 6 years

10 - 14 Lacs

Posted:1 day ago| Platform: Naukri logo

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Job Type

Full Time

Job Description

The Engineering Enablement team is responsible for providing tools, methodologies, and support to engineering teams to accelerate product development across the company. This position is for an opening in the Systems Verification and Validation (SVV) group within the Engineering Enablement organization in the Vertical BU. SVVs charter spans from defining, building and promoting the adoption of design verification tools and methodologies to executing high-value engagements that directly improve product outcomes and build long-term DV capability across ADI. SVV owns the entire DV technology spectrum, such as, UVM, Formal, FUSA, Security, Mixed-Signal, Emulation and Prototyping methodologies . This role is focused on driving Emulation and Prototyping.
 
Job Responsibilities :
  • Develop and deploy best in class Emulation/Prototyping tools and methodologies across ADI Product Lines as part of Verification eXcellence Program (VXP)
  • Develop and deploy Accelerated Verification IPs, Synthesizable BFMs and help in integration of memory models of various interfaces
  • Engaging with EDA vendors to effectively resolve tool & methodology issues meet ADI s requirements
  • Support the product lines in bring-up of new designs, debug issues and explore new methodologies that improve the overall verification flow
  • Training, deployment, and support of verification methodologies within ADI
Position Requirements :
  • Bachelors/master s degree in electrical/Electronics/VLSI with 3-6 years of experience
  • Experience in emulation/prototyping platforms such as Zebu/HAPs is highly preferred.
  • Experience in ASIC RTL to Emulation/Prototyping model creation, sanity development and Bring up
  • Experience in working with transactors and setting up runtime environment using C/C++/DPIs
  • Exposure to JTAG, UART and Speed Bridges (Ethernet/USB) validation is highly preferred
  • Expertise in one or more of scripting languages (shell, python, perl) is highly preferred
  • Proficient in SV, UVM, integration of third party VIPS, Accelerated VIPS is required
  • Exposure to VCS/Verdi for compilation and debugging issues
  • Experience with Vplan/Test plan development and development of verification environment from ground up is good
  • Experience in common communication protocols such as AMBA, I2C, SPI, and UART is an added advantage
  • Should be able to communicate technical details very effectively with both customers (product line teams) and peers
  • Work in collaboration with design/verification and customer teams
  • Good analytical and debugging skills

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