Lead ASIC - FPGA Verification Engineer

Position Overview

Boeing India Engineering seeks a Lead ASIC-FPGA Verification Engineer with considerable experience in design to support multiple product lines in commercial and defense electronics development.

Primary Responsibilities:

• Use high-level architectural documentation along with algorithm description and implement functions for test bench architecture and design.
• Develop models in System Verilog to verify design implementation and develop and run scripts and Make files.
• Leads analysis of customer and system requirements and development of architectural approaches and detailed specifications for various electronic products.
• Leads reviews of testing and analysis activity to assure compliance to requirements.
• Identifies, tracks and statuses technical performance measures to measure progress and ensure compliance with requirements.
• Leads activities in support of functional verification, simulation, emulation, safety and other technical services/methodologies.
• Proficient in crafting verification plan IPs/Subsystems.
• Coordinates engineering support throughout the lifecycle of the product.
• Plans research projects to develop concepts for future product designs to meet projected requirements.
• Works under minimal direction

Basic Qualifications (Required Skills/Experience):

• Bachelor, Master or Doctorate of Science degree from an accredited course of study, in engineering, computer science, mathematics, physics or chemistry is required
• 12 to 16 years of experience in Digital ASIC/FPGA verification.
• 4 or more years of concurrent exposure to Digital ASIC/FPGA Design.

Preferred Qualifications (Desired Skills/Experience):

• Experience leading development of architectural approaches from customer and system requirements.
• Experience identifying, tracking, and providing status of technical performance metrics to measure progress and ensure compliance with requirements.
• Experience directing a team of engineers for technical excellence.
• Experience developing and leading sophisticated and high data rate design verification bench.
• Expert in writing Universal Verification Methodology (UVM) sequences and virtual sequences and its concepts like Inheritance, Polymorphism, etc.
• Expert in using Universal Verification Methodology (UVM): Experience crafting drivers, monitors, predictors, and scoreboards.
• Work experience crafting a self-checking simulation test bench from scratch for SoCs/ASIC/FPGA.
• Work experience performing clock cross domain analysis (CDC).
• Expertise in verification working with internal/external VIPs, its development and evaluation with multiple vendors.
• In-hand depth upon System Verilog
• Work experience using Linux or Unix terminal commands.
• Experience using scripting languages: Make, Perl, Python, shell scripts, etc.
• Experience using Revision Control Systems: Subversion (SVN), CVS, Git.
• Good Understanding upon designing digital ASIC/FPGA architectural design documents (micro-architecture documents with timing diagrams, detailed design blocks, etc.).
• Good Understanding in deriving digital ASIC/FPGA requirements specification from higher-level (system or board-level) requirements specifications.
• Basic understanding upon concepts like RTL synthesis, Static Timing Analysis and correcting timing violations.
• Experience in Avionics protocols is a plus.

Typical Education & Experience:

Bachelor, Master or Doctorate of Science degree from an accredited course of study, in engineering, computer science, mathematics, physics or chemistry with 12 to 16 years of experience & Master's degree with 11+ years of experience.

Education

Bachelor's Degree or Equivalent Required