Senior Analog Design Engineer

Design and develop DDR I/O circuits targeting high performance and low power consumption Collaborate with cross-functional teams to efficiently integrate silicon IP into SoCs Perform circuit simulations and layout verification to ensure design precision Interface with internal engineering teams to troubleshoot and resolve design challenges Stay abreast of technological advancements and evolving industry standards (e.g., JEDEC) Document design methodologies for process improvement and knowledge sharing The Impact You Will Have: Propel next-gen silicon IP development with robust DDR I/O solutions Improve SoC integration speed and efficiency, aiding rapid product launches Advance innovation in chip design for smart technologies Ensure product quality meets or exceeds industry benchmarks Support Synopsys leadership in high-performance silicon IP Enable effective collaboration across expert engineering teams What You'll Need: BTech/MTech in Electrical Engineering or related discipline 3+ years of experience (MTech) or 5+ years (BTech) in CMOS circuit design and layout Strong grasp of deep submicron technologies and layout methodology Knowledge of JEDEC DDR interface standards Familiarity with ASIC design flow and ESD concepts is a plus Excellent problem-solving, analytical, and communication skills