RTL & Synthesis combined skills

The ideal candidate for this role should possess a Bachelor's or Master's degree in Electrical Engineering or a related field (BE/BTech/M.E/M.Tech). You should have excellent communication skills, both verbal and written. You should have 5-8 years of experience in RTL Design with exposure to synthesis or 8+ years of experience in RTL Design. A strong understanding of digital basics is essential, along with proficiency in RTL coding (Verilog), IP design, and RTL integration. Hands-on experience with LINT, CDC, and RDC is required, as well as experience in writing UPFs and CLP/VCLP checks. Familiarity with synthesis flow and validating design constraints is necessary, along with specific domain knowledge in ARM protocols, PCIe, Ethernet, RISC V, DDR, etc. Strong scripting knowledge is also preferred. As part of your responsibilities, you will need to understand the overall ASIC flow and effectively collaborate with multiple teams such as DV, DFT, Synthesis/Implementation, and PD teams. You should also have the ability to take on the role of a Technical Manager while maintaining hands-on contributions. Interested candidates are required to provide a detailed resume highlighting relevant experience and skills. This job falls under the category of VLSI (Silicon engineering) and is based in India, with locations in Bangalore and Hyderabad.,