RTL Design Engineer

Job Title:

Company:

Lead RTL Design Engineer

Key Responsibilities:

• Own

  microarchitecture and RTL development

  of complex IPs or subsystems.
• Lead block-level design from spec to synthesis and signoff.
  
• Drive RTL design using

  Verilog/SystemVerilog

  , ensuring quality and PPA targets.
• Guide and mentor junior RTL engineers across project cycles.
  
• Collaborate with architecture, verification, physical design, and firmware teams.
  
• Support STA, CDC, lint, synthesis, and design reviews.
  
• Contribute to methodology improvements and automation.
  

Required Skills:

• 10+ years of hands-on experience in

  RTL design and microarchitecture

  .
• Expertise in Verilog/SystemVerilog and digital logic design.
  
• Strong knowledge of

  AXI, AHB

  , and other AMBA protocols.
• Experience in

  low-power design

  , clock gating, UPF, and STA.
• Worked on

  at least 1–2 successful tape-outs

  in a lead role.
• Excellent debugging, review, and technical communication skills.
  

Good to Have:

• Experience with

  RISC-V, AI/ML accelerators, GPUs, or DSPs

  .
• Scripting knowledge: Python, Perl, or TCL.
  
• Familiarity with

  formal verification

  and

  FPGA prototyping

  .

Education:

B.E./B.Tech or M.E./M.Tech in ECE, Electrical, or Computer Engineering.
(Ph.D. is a plus)

Why Join Us?

• Work on

  cutting-edge technologies at advanced nodes

  (7nm/5nm/3nm).
• Lead high-impact projects with global teams.
  
• Grow into senior technical or architectural roles.
  

Apply Now:

Email: