R&D Engineer / VLSI Engineer ( ME Candidates Only)

Organization: Mirror Institute for Embedded Technology (MIET), Chennai
Location: 184/2, 3rd Floor, Chandamama Building, Arcot Road, Vadapalani, Chennai – 600026
(Landmark: Opp. Kamala Theater, Above Viveks Showroom)

Eligibility:

• Qualification: M.E. – VLSI Design / Embedded Systems / Power Systems / Power Electronics OR M.Sc. – Electronics
• Preference: Candidates from Anna University, Tamil Nadu (Regular) only
• Experience: Freshers & Experienced
• Academic Criteria: Min. 70% in UG and 65% in 10th & 12th

Role Overview:
Join MIET’s R&D division to learn, design, and innovate in VLSI and Embedded Technologies.Gain hands-on experience with FPGA/ASIC Design, Verilog/SystemVerilog, Xilinx & Mentor Graphics tools, and industry-grade projects.Opportunity to grow as a trainer, researcher, and innovator in advanced chip design and verification domains.

Skills Required:

• Strong fundamentals in Digital Electronics & VLSI
• Knowledge of Verilog / SystemVerilog, C / C++
• Familiarity with tools like Xilinx Vivado, ModelSim, Altera Quartus
• Good communication & mentoring skills
• Passion for learning and innovation

Contract: 3 Years |

Contact:
hrmirrorinstitute@gmail.com93809 48474 / 93819 48474

Job Type: Full-time

Pay: ₹18,000.00 - ₹22,000.00 per month

Work Location: In person