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Principal Engineer ASIC Digital Design IP Development

Principal Engineer ASIC Digital Design IP Development

Synopsys

8 - 14 years

25 - 30 Lacs

bengaluru

Posted:17 hours ago| Platform:

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Skills Required

synthesis lint r cdc static timing analysis simulation protocols system verilog

Work Mode

Work from Office

Job Type

Full Time

Job Description

Architect and design state-of-the-art RTL for DesignWare IP cores, focusing on protocols such as UALink, Ethernet, DDR, PCIe, and USB.
Create and document detailed architecture and micro-architecture specifications for medium to high complexity design components.
Perform individual contributor and technical lead responsibilities, including RTL coding, synthesis, CDC analysis, debugging, and test development.
Collaborate with verification teams on test planning, coverage planning, and verification closure to ensure high-quality deliverables.
Interact with customers to understand and translate specification requirements into robust design solutions.
Mentor and technically lead a team of designers, driving best practices and continuous improvement across global teams.

Job Requirements

Bachelor's or Master's degree in Electrical Engineering (BSEE/MSEE) with over 12 years of relevant ASIC design experience.
Expertise in protocols such as UALink, Ethernet, DDR, PCIe, USB, and hands-on experience with control path-oriented designs.
Proficiency in synthesizable Verilog/System Verilog RTL coding, simulation, and design verification tools.
Strong background in lint, CDC, synthesis, static timing analysis, formal checking, and P&R-aware synthesis flows.
Experience with revision control systems, scripting languages, and exposure to IP design quality processes.
Innovative problem-solver with a proactive approach and strong initiative.
Excellent communicator, able to bridge technical details with team members and customers.
Collaborative team player, thriving in diverse, global environments.
Mentor and leader, passionate about developing talent and sharing knowledge.
Detail-oriented professional committed to delivering high-quality, reliable solutions.

About Company

You'll join the DesignWare IP Design R&D team at Synopsys' Bangalore Design Center, collaborating with expert engineers across multiple global sites. The team is dedicated to developing high-performance IP cores for a broad range of applications, emphasizing technical excellence, innovation, and quality. You will work in an environment that encourages learning, growth, and leadership, contributing to products that shape the future of silicon design.

Rewards and Benefits:We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

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Principal Engineer ASIC Digital Design IP Development