Posted:1 day ago|
Platform:
On-site
Full Time
Develops pre silicon functional validation tests to verify system will meet design requirements Creates test plans for RTL validation defining and running system simulation models and finding and implementing corrective measures for failing RTL tests Analyzes and uses results to modify testingKnowledge of Verilog ,System Verilog, UVM Based Testbench developmentUnderstanding of code functional coverage system Verilog assertion codingGeneral Scripting and programming skills Python Per TCL etcFormal verification would be a plusIP Level testbench development using SV and UVMTestplan development using Verification planner, tracking and closer of code and functional coverageReq LocationSRR4 Bangalore
Define and develop test env to verify the IP/Sub System functionality.
Define Test plans and develop Tests contents.Define Checkers/monitors strategy.
Define and Develop Assertions.Define Cover points and analyze functional coverage with analysis.
Define Volume regressions strategy and run simulations followed by failure debugs.
Develop formal verification assertions, properties.
Define and perform Performance Verification.
Mentoring and coaching junior verification engineers.
Leadership to manage stake holders with end to end objectives in mind.
The candidate should have ability to work effectively with both internal and external teams/stakeholders. Should possess strong problem solving/communication skills. Should be a very good team player.
Intel
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