240 Pnr Jobs - Page 10

We are seeking a highly motivated and detail oriented Air Ticket Consultant to join our team Candidate must have knowledge of IATA, AMADEUS, GALILEO AND SABRE Candidate must have worked in air ticketing industry

Graduate Freshers can apply Undergraduate with minimum 1 year of exp required in backend Fres. Salary 22 k CTC Exp 24 k CTC Typing Speed 30WPM Both Sides Cabs Good communication needed Interested candidate contact Send me your resume 9717700137 Required Candidate profile Contact HR Sonu Chaurasiya 9717700137 Skill seekers consultancy Towers, 401, 1, pvr, Vikaspuri, New Delhi, Delhi 110018

About The Role : Role Purpose: A Business Finance Manager role requires working with cross-functional teams Do: - Co-own the financial plan of the portfolio along with the portfolio lead. - Revenue governance (including client interactions for deal closures and contracting; forecasting, revenue recognition) - Margin Governance (including cost take out initiatives, systemic and sustainable cost reduction analysis). - Working capital governance (including unbilled reduction, timely invoicing, and collection, improving debt ageing and PDD). - MIS for the business unit including cost pyramid analytics, revenue leakage vs order book. - Critical attributes to success would be strong communication, cadence, and resilience. - Commercial Structuring and Deal pricing for multiple lines of business

Job Purpose "This position is open with Bajaj Finance ltd." To handle and provide solution for a transactional activities of field team and making sure the implementation of projects are end to end satisfying the requirement. Duties and Responsibilities 1.Resolving SFDC functions related issues 2.Resolving BRE level issues 3.Educating internal and field teams on issues due to training requirements 4.Constant observations on the issues raised by the field team 5.Raising regular IT request to resolve issues 6.Constant communication between IT and Product teams to identify the changes 7.Attending bi-weekly meetings with IT to find the bigger solution 8.Find solutions to the repetitive problems and submit BRD 9.Interacting with field teams to identify the exact issues Required Qualifications and Experience ducational Qualifications a)Graduate or equivalent b)1+ years of experience Finance industry support of system c)Well versed in MS Office d)Agile ability on the work timings

Primary & Mandatory Skill: Client Round (Yes/ No):Yes Location Constraint if any:Bangalore/Pune Shift timing:General

About The Role : Require Extraction expert with 8+ years' experience. The candidate will be expected to perform Development/support for extraction solutions for gate level and/or transistor level to build high quality PDK on STARRC/QRC. Development/support of ICV/Calibre/Pegasus runset (rule deck) for parasitic extraction, correlate parasitic coming from different extraction flows, assume ownership of entire LVS/extraction flow, working closely with various design/development groups. Perform in a dynamic and challenging environment with drive and creativity. Candidate is expected to have great stake holder management and leadership skill. Qualifications B.tech or M.tech with 8+ years of experience in runset development/QA on ICV/Calibre/Pegasus tools/flow. Expertise in Parasitic extraction tools like StarRC, QRC , xACT. Strong debugging and scripting skills. Strong team working and leadership skills. Inside this Business Group As the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support. Employees in theTechnology Development and Manufacturing Groupare part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore's Law to bring smart, connected devices to every person on Earth.

About The Role : Creates bottomsup elements of chip design including but not limited to FET, cell, and blocklevel custom layouts, FUBlevel floor plans, abstract view generation, RC extraction and schematictolayout verification and debug using phases of physical design development including parasitic extraction, static timing, wire load models, clock generation, customer polygon editing, autoplace and route algorithms, floor planning, fullchip assembly, packaging, and verification. Troubleshoots a wide variety up to and including difficult design issues and applied proactive intervention. Schedules, staffs, executes and verifies complex chips development and execution of project methodologies and/or flow developments. Requires expansive knowledge and practical application of methodologies and physical design. Qualifications You should possess a BE or BTech or equivalent technical degree in Electronics Electrical engineering with 2-3+ years experienceExperience Skills: SoC Place and Route Physical design Layout convergence experience. Basic programming skills UNIX shell script Tcl Perl Python Additional qualifications include Proficiency in multiple levels of layout design which includes partitions, subsystems Proficiency in floor planning activities which include Par unit level assembly routing and integration of partition, section, custom blocks in to the FC floorplan Ability to comprehend issues of RC delay electromigration self heating and cross capacitance Ability to recognize failure prone layout structures and proactively contact engineers for guidance and produce electrically robust layout Inside this Business Group The Client Computing Group (CCG) is responsible for driving business strategy and product development for Intel's PC products and platforms, spanning form factors such as notebooks, desktops, 2 in 1s, all in ones. Working with our partners across the industry, we intend to deliver purposeful computing experiences that unlock people's potential - allowing each person use our products to focus, create and connect in ways that matter most to them. As the largest business unit at Intel, CCG is investing more heavily in the PC, ramping its capabilities even more aggressively, and designing the PC experience even more deliberately, including delivering a predictable cadence of leadership products. As a result, we are able to fuel innovation across Intel, providing an important source of IP and scale, as well as help the company deliver on its purpose of enriching the lives of every person on earth.

Responsibilities Perform Sub system level floor planning, placement, and routing for high-performance microprocessor design. Collaborate with cross-functional teams to achieve design goals. Close the design to meet timing, power, and area requirements. Implement engineering change orders (ECOs) to rectify functional bugs and timing issues. Ensure the quality and efficiency of the RTL to GDS2 implementation process. Required education Bachelor's Degree Preferred education Bachelor's Degree Required technical and professional expertise 8+ years of industry experience Good knowledge and hands on experience in physical design , timing and methodology which include logic synthesis, placement, clock tree synthesis, routing , post route closure. Should be knowledgeable in physical verification ( LVS,DRC.. etc) ,Noise analysis, Power analysis and electro migration . Good knowledge and hands on experience in static timing analysis (closing timing at chip level) Good understanding of timing constraints . Should have experience in handling asynchronous timing, multiple corner timing closure. Preferred technical and professional experience Automation skills in PERL ,SKILL and/or TCL

About The Role : Experience in Mixed-Signal layout design, holding bachelors degree in electrical/Electronic Engineering. To work independently on block levels analog layout design from schematic, estimating the Area, Optimizing Floorplan, Routing and Verifications. Firsthand experience in Critical Analog Layout design of blocks such as Temperature sensor, Serdes, PLL, ADC, DAC, LDO, Bandgap, Ref Generators, Charge Pump, Current Mirrors, Comparator, Differential Amplifier etc., Good at LVS/DRC debugging skills and other verifications for lower technology nodes like 14nm FinFet and below. Good understanding of Matching, EM, ESD, Latch-Up, Shielding, Parasitic and short channel concepts. Familiar with EDA tools like Cadence VLE/VXL, PVS, Assura and Calibre DRC/ LVS is a must. Understanding layout effects on the circuit such as speed, capacitance, power and area etc., Ability to understand design constraints and implement high-quality layouts. Multiple Tape out support experience will be an added advantage. Good people skills and critical thinking abilities to resolve the issue technically, and professionally. Excellent communication. Responsible for timely execution with high quality of layout design. Primary Skills Analog Layout Process or technology experience:TSMC 7nm, 5nm, 10nm,28nm , 45nm,40nm EDA Tools: Layout Editor:Cadence Virtuoso L, XL Physical verification :DRC, LVS, Calibre Secondary Skills IO layout

Overview: TekWissen Group is a workforce management provider throughout India and many other countries in the world. The below client is a leading Product Engineering Services company specializing in Semiconductor Design Services, Embedded Systems, Digital Solutions, Artificial Intelligence, Machine Learning, IoT, Networking, and Robotics. Job Title: PD with Synthesis Location: Bangalore, India Years of exp: 3+ Job Description Front-End Implementation Requirements. PD: We are looking for expertise in Pre-layout STA, CLP, PNR, STA, FV, CLP timing constraints, and Genus, with candidates who are willing and able to work on synthesis. Synthesis: We are looking for expertise in Synthesis, FV, CLP, and Genus, with candidates who are willing and able to work on synthesis. TekWissen Group is an equal opportunity employer supporting workforce diversity.

This role does design and layout of complex VLSI (very large scale integration) circuits using graphic editing tools in cutting edge technological nodes. A major portion of the job is in creation of new physical design data from concepts, partial schematics or a working knowledge of overall requirements. Responsibilities include checking the design integrity with respect to semiconductor ground rules and the logical function of the circuit. Symbolic circuit data (schematics) are converted to physical shapes which represent the semiconductor process. The role ranges from manual shapes and checking tool manipulations to extended team coordination and methodology creation. The employee guides functional objectives or technologies. Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise 6-8 Years of relevant experience in Memory Layout design for blocks like Caches, CAMs, Register files, multiport register Files, Compilers etc.Should be in a position to work hands on on memory IPs, help generate and curate new ideas for layout designing, innovate new ways of layout designing, bring leadership into work and have growth mindset and have openmindedness to automation ideas; Excellent communication skills to be able to work with crosssite designers, EDA for development and curation of new tools needed for work. Should be able to understand various memory architechtures, experience in bit cells layouts, compiler layout design; Should have hands on experience in Finfets, GAA etc. Should have had experience in technology nodes below 7nm; LVS, DRC, Antenna, DFM, EM, IR, Methodology check debugging and fixing is a must; Leadership to drive collaborative initiatives with cross teams; SRAM designing experience is an added advantage Preferred technical and professional experience Scripting to ease deliverables is an added advantage. Automation skills in PERL, Python ,SKILL and/or TCL Environment: Professional knowledge related to incumbent's function/business unit and its processes.Communication/Negotiation: Advise other professionals. Effectively utilize group dynamics. Negotiate to define approaches and goals.Problem Solving: Recognize complex problems related to functional objectives. Analyze situations and implement solutions, or develop new system elements, procedures or processes. Creativity and judgment applied to developmental work on different projects within the business environment. Contribution/Leadership:Provides ongoing technical /operational guidance to lead professional work teams, conducts special projects, or manages department(s) (national or international). Understand department/ functional mission and vision. Defines and decides objectives within specified business concept or project and may have responsibility for tools and assigned resources. Utilizes expertise to directly influence people outside department or function. Sometimes no precedent exists.Impact on Business/Scope:Accountable for department results and for activities and/or projects involving multi-functional teams. Regularly participates in overall functional program planning. Activities are subject to business measurements, impact customer satisfaction, and impact project costs or expenses.

Responsibilities The India System design team is responsible to own and deliver System design milestones for IBM POWER and mainframe platforms. The team collaborates with Global System design & development teams and stakeholders. As a Physical Design Engineer for PCB, the candidate must have experience to deliver complete custom PCB card designs, which would be used for our hardware products. Responsibilities As Physical Design Engineer, the responsibilities include Work with Card Logic Design and Card Signal Integrity Engineers to deliver complete custom PCB card designs. Implement feedback from bring up efforts for modifications to existing card layouts. Work in the Cadence design space to layout, wire multi-layer PCB designs. Create EC list of changes from one release to the next. Lead Physical Design reviews to support Gerber release schedules Generate and maintain documentation for PCB card designs Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise Bachelors in Electrical/Electronics Engineering Experience with CAD tools for PCB design Programming experience (Python, SKILL, etc.) Preferred technical and professional experience Familiarity with server design and architecture. Experience with Cadence tools for PCB design Experience with PCB fabrication processes Multi-disciplinary engineering experience (Mechanical, Thermal, etc.) Experience with Git, GitHub, or other software repository versioning tools

Responsibilities 1. Hands on work on custom layout for analog blocks like High Speed SerDes and General purpose IO designs with Cadence Virtuoso on latest technologies like 5nm and below and also take leadership roles in delivery of IPs 2. Work on Floor planning, power design, signal routing strategy, EMIR awareness andparasitic optimisations 3. Understand and apply analog Layout techniques to ensure the design meets performance with minimum possible area and good yield. 4. Participate in building and enhancing layout flow for faster, higher quality design process. 5. Checking physical verifications like DRC/LVS/ERC/ANT/DFM and other IBM internal checks 6. Collaborate with Circuit Designers to solve challenging problems 7. Writing SKILL/PYTHON scripts to automate repetitive tasks 8. Work with Place and Route engineer to integrate custom macros into top level. 9. Able to perform design reviews across global team 10. Work closely with required global teams to ensure the success of the whole product. 11. Leadership in delivery of macros we plan to own from India Job requirements: 1. Experience in doing layouts for analog blocks like SerDes, ADCs, DACs, LDOs, PLLs, BGAP & amplifiers etc. 2. Experience in designing layouts for high-speed circuits is a plus. 3. Layout experience in the following technology nodes:3nm, 5nm and 7nm FinFET. 4. Good team worker with multi-discipline, multi-cultural and multi-site environments 5. Strong fundamental knowledge in semiconductor device physics, layout principles, IC reliability and failure mechanisms 6. Good problem-solving skills are essential where problems are analysed upfront, identifying gaps, and providing optimum solutions 7. Knowledge in Skill/perl/tcl/Python scripting is a plus. Required education Bachelor's Degree Preferred education Bachelor's Degree Required technical and professional expertise The Analog layout design engineer with experience in next generation Ultra high speed serial IO link (HSS) interface for Cognitive, ML,DL, and data center applications. The engineer needs to have knowledge in the design and development full custom analog layouts for ultra high speed 32G/50G/112G IO link interfaces. Preferred technical and professional experience Experience in 7 and 14 nm analog layout design. Working on Cutting edge technology and HSS domain . Quick learner, deep layout design knowledge, problem solving skills and good communication skills with cross teams across the Geos.

Responsibilities In this role, you are expected to Efficient in LVS/DRC Runset development Hands on experience in working on LVS and DRC runset development and support Knowledge/Exposure in lower process node Have excellent debugging skills. Have strong interpersonal skills needed to coordinate deliverables and requirements from several areas within and outside of the organisation. Have familiarity with ICV , Calibre Physical Design Verification Tools Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise 2-5 years of Chip Layout and Runset Coding (ICV / Calibre ) Chip layout fundamentals (understanding the layers and how they connect and the rules on sizing and spacing and the electrical connectivity logic) Runset coding in general, ICV pxl in particular Basic SKILL code (for interfacing with Virtuoso) Basic TCL for interfacing with Custom Compiler and ICV Basic Python scripting VLSI knowledge Proven problem-solving skills and the ability to work in a team environment are a must EDA tool development experience Preferred technical and professional experience Cadence,Synopsys,VLSI Knowledge

Responsibilities 1. Hands on work on custom layout for analog blocks like High Speed SerDes and General purpose IO designs with Cadence Virtuoso on latest technologies like 5nm and below and also take leadership roles in delivery of IPs 2. Work on Floor planning, power design, signal routing strategy, EMIR awareness andparasitic optimisations 3. Understand and apply analog Layout techniques to ensure the design meets performance with minimum possible area and good yield. 4. Participate in building and enhancing layout flow for faster, higher quality design process. 5. Checking physical verifications like DRC/LVS/ERC/ANT/DFM and other IBM internal checks 6. Collaborate with Circuit Designers to solve challenging problems 7. Writing SKILL/PYTHON scripts to automate repetitive tasks 8. Work with Place and Route engineer to integrate custom macros into top level. 9. Able to perform design reviews across global team 10. Work closely with required global teams to ensure the success of the whole product. 11. Leadership in delivery of macros we plan to own from India Job requirements: 1. Experience in doing layouts for analog blocks like SerDes, ADCs, DACs, LDOs, PLLs, BGAP & amplifiers etc. 2. Experience in designing layouts for high-speed circuits is a plus. 3. Layout experience in the following technology nodes:3nm, 5nm and 7nm FinFET. 4. Good team worker with multi-discipline, multi-cultural and multi-site environments 5. Strong fundamental knowledge in semiconductor device physics, layout principles, IC reliability and failure mechanisms 6. Good problem-solving skills are essential where problems are analysed upfront, identifying gaps, and providing optimum solutions7. Knowledge in Skill/perl/tcl/Python scripting is a plus. Required education Bachelor's Degree Preferred education Bachelor's Degree Required technical and professional expertise The Analog layout design engineer with experience in next generation Ultra high speed serial IO link (HSS) interface for Cognitive, ML,DL, and data center applications. The engineer needs to have knowledge in the design and development full custom analog layouts for ultra high speed 32G/50G/112G IO link interfaces. Preferred technical and professional experience Experience in 7 and 14 nm analog layout design. Working on Cutting edge technology and HSS domain . Quick learner, deep layout design knowledge, problem solving skills and good communication skills with cross teams across the Geos.