Physical Design Engineer Memory Layout (TSMC)

Role Overview: As a Physical Design Engineer specializing in memory layout within leading TSMC process technologies (7nm and below), you will be responsible for designing and developing memory layouts such as SRAM, ROM, and Register Files. Your focus will be on optimizing performance, area, and power efficiency to ensure design integrity and compliance with foundry requirements. This role will allow you to collaborate with global teams and work on cutting-edge technology nodes. Key Responsibilities: - Design and develop memory layouts in advanced process nodes (TSMC 7nm, 5nm, 3nm, 2nm). - Implement layout including floorplanning, placement, routing, and parasitic extraction. - Collaborate with circuit designers to ensure layout functionality, performance, and reliability. - Conduct DRC, LVS, and EM/IR checks for design integrity and compliance. - Work with foundry teams to resolve layout-related issues and optimize for manufacturability. - Provide support for tape-out and post-silicon validation. Qualifications Required: - 2+ years of experience in memory layout design for advanced nodes. - Strong expertise in TSMC technologies (7nm and lower - 5nm, 3nm, 2nm). - Proficiency with industry-standard EDA tools (Cadence Virtuoso, Synopsys, Mentor, etc.). - Solid understanding of DRC/LVS/PEX verification methodologies. - Experience in memory IP development (SRAM, ROM, cache, etc.). - Knowledge of power, performance, and area (PPA) optimization techniques. - Strong problem-solving skills and attention to detail. - Good communication and teamwork abilities. Additional Company Details: The company is in the Semiconductor industry and the work location is in Bangalore, India. This is a full-time, permanent position that requires in-person work.,