Physical Design Engineer Memory Layout (TSMC) Org Linked

2.0 - 6.0 years

0 Lacs

karnataka

On-site

Role Overview: As a Physical Design Engineer specializing in memory layout within leading TSMC process technologies (7nm and below), you will be responsible for designing and developing memory layouts such as SRAM, ROM, and Register Files. Your focus will be on optimizing performance, area, and power efficiency to ensure design integrity and compliance with foundry requirements. This role will allow you to collaborate with global teams and work on cutting-edge technology nodes. Key Responsibilities: - Design and develop memory layouts in advanced process nodes (TSMC 7nm, 5nm, 3nm, 2nm). - Implement layout including floorplanning, placement, routing, and parasitic extraction. - Collaborate wi...

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Principal Physical Design Lead SiFive

12.0 - 16.0 years

0 Lacs

karnataka

On-site

About SiFive SiFive, the pioneers who introduced RISC-V to the world, are revolutionizing the future of computing by harnessing the boundless potential of RISC-V for the most high-performance and data-intensive applications globally. SiFive's unparalleled computing platforms continue to empower leading technology firms worldwide to innovate, optimize, and deliver cutting-edge solutions across various chip design segments, including artificial intelligence, machine learning, automotive, data center, mobile, and consumer electronics. With SiFive, the future of RISC-V knows no bounds. At SiFive, we are eager to engage with talented individuals who share our fervor for driving innovation and mak...

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Senior Principal Design Engineer Cadence Design Systems

10.0 - 18.0 years

3 - 13 Lacs

Bengaluru / Bangalore, Karnataka, India

On-site

BE/BTECH/ME/MTECH Or Equivalent Degree EXP:10-18yrs Primarily working for Roadmap project MRDIMM Controller for CHI Address channel Multiplexing RTL Design, Verification and Synthesis Support. Work to achieve MRDIMM Controller for CHI Address channel Multiplexing Feature s Optimal PPA (Performance, Timing and Area)

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Sr/Staff AE for Physical Implementation RTL-GDS Synopsys (India) Private Limited

10.0 - 12.0 years

10 - 12 Lacs

Bengaluru / Bangalore, Karnataka, India

On-site

Working on latest Synopsys implementation technologies ( Machine Learning , Physical Synthesis , Multi Source CTS etc ) to solve complex PPA challenges faced by Synopsys customers. Working on benchmarks to displace competition implementation solutions Working with customers to develop and debug RTL-GDS implementation methodologies and flows. Providing technical solutions by identifying the design and/or EDA tool issues and provide appropriate solution for customers Effectively translate the findings into requirements for R&D to improve both tool behavior with enhancements as adaptive long-term solutions. Involved in deployment of new technologies on latest EDA versions and enable customers t...

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Digital Flow Solutions Engineer Cadence Design Systems

1.0 - 3.0 years

3 - 13 Lacs

Bengaluru / Bangalore, Karnataka, India

On-site

Interfacing with customers regarding digital reference flows, including Synthesis Floorplanning Clock tree synthesis Power planning Place and route Timing closure Creating baseline flows to be used by customers as starting point for digital implementation Performing digital place and route and sign-off on small customer designs Creating documentation PPA optimization Bachelor s degree with at least 1-3 years of design/EDA experience or Master s degree. Strong knowledge of Digital Design Fundamentals, Semiconductor Fundamentals and Static Timing Analysis Prior experience with ASIC digital implementation flows and EDA tools is required; Experience with advanced nodes (7nm and below) preferred....

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Sr/Staff AE For Physical Implementation RTL-GDS Synopsys

10.0 - 15.0 years

3 - 13 Lacs

Bengaluru / Bangalore, Karnataka, India

On-site

Responsibilities: As Senior Staff Application Engineer (AE) , you will be Working on latest Synopsys implementation technologies ( Machine Learning , Physical Synthesis , Multi Source CTS etc ) to solve complex PPA challenges faced by Synopsys customers. Working on benchmarks to displace competition implementation solutions Working with customers to develop and debug RTL-GDS implementation methodologies and flows. Providing technical solutions by identifying the design and/or EDA tool issues and provide appropriate solution for customers Effectively translate the findings into requirements for R&D to improve both tool behavior with enhancements as adaptive long-term solutions. Involved in de...

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