Physical Design Engineer

Role & responsibilities

• Good Experience in Logical/Physical/Low power Synthesis.
• Good understanding of Logic Equivalence and Low Power checks at SoC level.
• Developing and validation of Floor Plan and PG grid for different technology nodes
• Should have a good understanding of Timing constraints, UPF and IP/Macro collaterals.
• Working knowledge of multi power domain designs.
• Good Knowledge in Place & Route and expertise in Optimization Techniques to achieve the best Performance/Power/Area of the designs.
• Work experience in SoC Power/IR signoff (static/dynamic/EM), drive power optimization at various stages of design to produce best PPA.
• Working with SOC and Packaging Teams on Bumps Assignments / RDL Enablement / Pkg Routing Optimizations to improve overall PDN Design
• Experience with all aspects of Static Timing Analysis, multi-corner and multimode timing closure for complex SoC.
• Good understanding of library, derates, AOCV/POCV and intricate dependency on timing analysis.
• Work experience in SoC Power/IR signoff (static/dynamic/EM), drive power optimization at various stages of design to produce best PPA.
• Working with SOC and Packaging Teams on Bumps Assignments / RDL Enablement / Pkg Routing Optimizations to improve overall PDN Design
• Experience with all aspects of Static Timing Analysis, multi-corner and multimode timing closure for complex SoC.
• Good understanding of library, derates, AOCV/POCV and intricate dependency on timing analysis.