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PE Logic Design Professional

PE Logic Design Professional

Rambus Chip Technologies

2 - 3 years

10 - 14 Lacs

Bengaluru

Posted:1 day ago| Platform:

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Skills Required

Semiconductor DFT static timing analysis Project management Analog CAD Perl MTS Physical design Recruitment

Work Mode

Work from Office

Job Type

Full Time

Job Description

Rambus, a premier chip and silicon IP provider, is seeking to hire an exceptional Lead MTS Physical Design Engineer to join our MIC Design IDC team in Bangalore. Candidates will be joining some of the brightest inventors and engineers in the world to develop products that make data faster and safer.

Rambus offers a flexible work environment, embracing a hybrid approach for the majority of our office-based roles. We encourage employees to spend an average of at least three days per week working onsite, allowing for two days of remote work.

Responsibilities

Complete ownership of Static timing analysis at full chip level for high speed mixed signal design
Experience doing multi-mode multi-corner (MMMC) timing and power analysis using primetime/Tempus.
Experience in DMSA/Tweaker ECO flows for PPA improvements.
Experience in manual timing fixes, ECO generation for MCMM mode corners.
Good understanding of SDC constraints and able to translate timing requirements into constraints.
Responsible for integrating the blocks, analog Ip s for full chip timing analysis.
we'll aware of place and route methodologies and hands on experience with timing convergence
Good communication skill to negotiate with top level for convergence.
Work closely with Project leader for creating schedule, tracking and raising issues / risks to project management.
Participate in Mentoring new joiners in the group on technical skills.
Provide inputs for CAD/DA team from Design Implementation perspective.
Work closely with Logic design team and Analog teams to provide inputs from physical design and STA.
Work closely with DFT team on scan aspects and provide inputs from physical design.
Continuously work on methodology and productivity improvements.

Qualifications

Must have at least 8 years should be related to STA/Synthesis .
Must have Involved in high Speed design tape-outs and constraint development across modes.
Must have detailed knowledge of Constraints , Signoff closure methodology for STA and RTL2GDS flow is desired
Experience in Tcl/Tk, PERL is a Plus.

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Rambus Chip Technologies

Semiconductor Manufacturing

San Jose CA

501-1000 Employees

2 Jobs

Key People

Luc Seraphin

CEO
Diana W. McKenzie

CFO
Sanjay Sarma

CTO

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PE Logic Design Professional