Posted:1 day ago|
Platform:
Work from Office
Full Time
PD
The candidate will be responsible for implementing the place and route of design blocks including floorplanning, placement, clock tree building, routing, timing optimizations, DRC, LVS fixing, IR drop analysis, Formal verification, power intent checks etc . The candidate will also be responsible for block level physical design closure in terms of timing, power, DRC/LVS etc.
Full Chip Floorplan:
Bus planning
Pin assignments
Tile area allocations
Repeater planning and Feedthrough push
Full chip Tile PnR
7-10 yrs of experience, preferably with AMD experience
ACL Digital
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