Part-Time Design Verification Engineer (SoC/System-Level)

Abidott Solutions (OPC) Private Limited

0 years

0 Lacs

kerala india

Posted:1 month ago| Platform:

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Skills Required

design verification debugging systemverilog architecture support regression python perl ethernet

Work Mode

On-site

Job Type

Part Time

Job Description

Design Verification Engineer

Key Responsibilities

Perform SoC/system-level verification using SystemVerilog and UVM.
Develop and maintain testbench architecture and verification infrastructure.
Integrate VIP and support C-based verification flows.
Conduct functional, regression, and system-level validation.
Debug issues across RTL, firmware, and system components.

Required Skills

Strong expertise in
SystemVerilog / UVM
.
Proficiency in
Python, Perl, or Shell scripting
.
Experience with
C-based verification
.
Strong debugging skills and understanding of complex SoC environments.

Preferred Skills

Knowledge of
PCIe, HBM, Ethernet, or D2D
technologies (added advantage).

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Abidott Solutions (OPC) Private Limited

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Part-Time Design Verification Engineer (SoC/System-Level)