NoC - Design Verification Engineer

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About the Role

NoC Design Verification Engineer

Key Responsibilities

• Develop and execute

  comprehensive verification plans

  for NoC architectures and subsystems.
• Design and maintain

  constrained-random and directed testbenches

  using UVM/OVM methodologies.
• Build scalable, reusable, and automated

  verification environments and scripts

  to improve efficiency and coverage.
• Collaborate closely with

  architecture, RTL design, and validation teams

  to ensure full functional and performance verification.
• Analyze and debug

  complex design and simulation issues

  using industry-standard tools.
• Drive

  coverage closure (functional, code, and assertion coverage)

  to meet verification goals.

Required Skills & Experience

• 512 years

  of experience in

  design verification

  , specifically in

  Network on Chip (NoC)

  technologies.
• Deep understanding of

  NoC protocols, interconnects, arbitration, and routing algorithms

  .
• Hands-on experience with

  SystemVerilog

  ,

  UVM/OVM

  , and modern verification methodologies.
• Proficient in

  SoC/ASIC design and verification flows

  , with strong debug and analysis skills.
• Solid experience with simulation and verification tools such as

  VCS, Questa, Verdi, or similar

  .
• Strong scripting skills (Python, Perl, Tcl, or Shell) for automation and productivity enhancement.
  

Eligibility Criteria

• Mandatory:

  Candidates

  must be currently working or have prior experience

  in

  product-based companies

  .
• Excellent communication, documentation, and interpersonal skills.
  

Why Join Us?

• Work on

  cutting-edge technologies

  at the heart of next-gen SoCs.
• Be part of a

  high-performance engineering team

  in a product-centric environment.
• Competitive compensation with

  industry-leading benefits

  .
• Opportunity to make a

  real impact on silicon innovation and performance

  .

Apply Now

we'd love to hear from you!