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IP / SoC RTL Senior / Lead Design Engineer

6 - 8 years

6 - 10 Lacs

Hyderabad Telangana India

Posted:16 hours ago| Platform: Foundit logo

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Skills Required

Design Engineering ASIC Design RTL Coding Microarchitecture

Work Mode

On-site

Job Type

Full Time

Job Description

IP / SoC RTL Senior / Lead Design Engineer

Responsibilities

  • Responsible for

    IP / sub-system level micro-architecture development

    and

    RTL coding

    .
  • Prepare

    block/sub-system level timing constraints

    .
  • Integrate

    IP/sub-system

    into larger designs.
  • Perform

    basic verification

    in either an IP verification environment or on an FPGA.

Skills

  • Expertise in

    Verilog

    is a must.
  • Experience in

    Logic design, micro-architecture, and RTL coding

    is essential.
  • Knowledge of

    AMBA protocols - AXI, AHB, APB

    .
  • Experience in

    synthesis

    and a strong understanding of

    timing concepts for ASIC

    development.
  • Hands-on experience in

    multi-clock designs

    and

    asynchronous interfaces

    is a must.
  • Experience with tools used in all phases of ASIC development, such as

    Lint, CDC, and Simulation

    .
  • Knowledge of

    low power concepts

    is a plus.
  • Experience in designing controllers for complex protocols like

    DDR, USB, or PCIe

    is a plus.

Qualifications

  • B.Tech. or M.Tech. with relevant experience.
  • Immediate availability is preferred

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