991 Floor Planning Jobs - Page 40

Role Purpose The purpose of this role is to perform the development of VLSI system by defining the various functionalities, architecture, layout and implementation for a client Do 1. Conduct verification of the module/ IP functionality and provide customer support a. Understand the architecture of the module or the IP and create verification environment and the development plan as per Universal Verification Methodology b. Create test bench development and test case coding of the one or multiple module c. Write the codes or check the code as required d. Execute the test cases and debug the test cases if required e. Conduct functional coverage analysis and document the test cases including fai...

Must Have Skills Floor Planning/Innovus/Fusion Compiler Good to have Experience on programming in Tcl/Tk/Perl. Physical Design Methodologies and submicron technology of 28nm and lower technology nodes. Mandatory Skills: VLSI Physical Place and Route.Location- Bangalore/ Pune/ Hyderabad/ Kochi

SUMMARY Part-Time Weekend Job Join Leading Food & Beverage Industry Team in Bangalore Job Role: Weekend Supporting Staff Company: Food & Beverage Industry Location: Bangalore Work Locations: Lulu Mall (Rajajinagar) Phoenix Marketcity (Whitefield) Shift Timing: 12:00 PM 5:00 PM Work Days: Saturday and Sunday Estimated Monthly Earnings: 3,000 3,500 Work 4 5 hours and earn extra income every weekend Key Responsibilities: Support kitchen and floor staff Serve starters, beverages, and non-vegetarian items (including chicken) Maintain cleanliness in service and dining areas Ensure smooth dining operations Requirements: No prior experience required (orientation provided) Must be energetic, discipli...

Job Description: We are looking for an experienced Physical Design Engineer with strong expertise in EMIR analysis and end-to-end RTL to GDSII flow. The ideal candidate should have hands-on experience in physical design, power integrity, and timing closure at advanced process nodes. Key Responsibilities: Handle complete RTL to GDSII implementation Perform EMIR (Electro migration and IR drop) analysis and closure Conduct timing analysis , power planning , and floor planning Run and debug DRC , LVS , and STA reports Work on advanced technology nodes (e.g., 7nm, 5nm ) Collaborate with cross-functional teams (FE, DFT, verification, etc.) Automate flows using Python , TCL , or Perl Required Skill...

Expectations/ Requirements: l Key account Manager is principally responsible for Signing New Logos/ Merchants/Brands from Large Enterprise / Corporate Accounts. l The BDM achieves these goals by creating Funnel and Closure of accounts. Superpowers/ Skills that will help you succeed in this role: l Adaptability: Attitude of optimism and can-do orientation with ability to think creatively and navigate successfully past barriers and obstacles l Focus through the Noise: Ability to tune out distractions to focus work on priority goals and tasks l Persuasion: Ability to present concepts, ideas and proposals in a manner that is perceived positively by and clearly resonates with intended audiences a...

Job Description: We are seeking an experienced Physical Design Engineer with strong expertise in VCLP (Voltage-Controlled Low Power) techniques and full flow RTL to GDSII implementation. Key Responsibilities: End-to-end ownership of physical design flow from RTL to GDSII VCLP implementation and optimization (highly important) Block-level and full-chip physical design Perform timing analysis , DRC/LVS checks , and power optimization Collaborate with front-end, verification, and DFT teams for successful tape-out Must-Have Skills: Strong hands-on experience in VCLP RTL to GDSII implementation EDA tools (Cadence Innovus, Synopsys ICC2, PrimeTime, Mentor Calibre) Scripting languages: Python, TCL,...

The analyst will produce high-quality written content that communicates complex market dynamics clearly. Support insights with compelling visuals such as charts and graphs. The candidate will engage regularly with clients through calls, meetings, conferences, and events delivering tailored insights, explaining methodologies, and articulating value propositions. Responsibilities The analyst will conduct power modelling for power markets to deliver short-term market forecasts in client-facing reports. Key considerations in modelling may include, but are not limited to: Capacity build-up. Thermal fuel switching. Temperature-adjusted power demand. Power market mechanisms and price settlement met...

We are seeking a highly skilled and experienced Physical Design Engineer to join our team. The ideal candidate will have hands-on experience in chip-level and block-level physical design, timing closure, and signoff processes. This role requires proficiency in industry-standard tools and scripting, along with a strong understanding of design constraints and methodologies. Key Responsibilities: Perform chip-level floorplanning, partitioning, timing budget generation, and power planning.Execute top-level place and route (PnR), clock tree synthesis (CTS), block integration, and ECO generation.Handle block-level implementation from netlist to GDSII.Drive timing closure for high-frequency blocks ...

: To work independently on block/IP levels analog layout design from schematic. Estimating the Area, Optimizing Floorplan, Routing and Verifications. Good at LVS/DRC debugging skills and other verifications for lower technology nodes like 5,7,10, 14nm FinFet and below. Good understanding of Matching, EM, ESD, Latch-Up, Shielding, Parasitic and short channel concepts. Familiar with EDA tools like Cadence Virtuoso Editor & Calibre RVE Good interpersonal skills and critical thinking abilities to resolve the issue technically, and professionally. Key Responsibilities: Independently execute block/IP-level analog layout from schematics, including area estimation, floorplan optimization, routing, a...

We are seeking a highly skilled and experienced Physical Design Engineer to join our team. The ideal candidate will have hands-on experience in chip-level and block-level physical design, timing closure, and signoff processes. This role requires proficiency in industry-standard tools and scripting, along with a strong understanding of design constraints and methodologies. Key Responsibilities: Perform chip-level floorplanning, partitioning, timing budget generation, and power planning.Execute top-level place and route (PnR), clock tree synthesis (CTS), block integration, and ECO generation.Handle block-level implementation from netlist to GDSII.Drive timing closure for high-frequency blocks ...

: To work independently on block/IP levels analog layout design from schematic. Estimating the Area, Optimizing Floorplan, Routing and Verifications. Good at LVS/DRC debugging skills and other verifications for lower technology nodes like 5,7,10, 14nm FinFet and below. Good understanding of Matching, EM, ESD, Latch-Up, Shielding, Parasitic and short channel concepts. Familiar with EDA tools like Cadence Virtuoso Editor & Calibre RVE Good interpersonal skills and critical thinking abilities to resolve the issue technically, and professionally. Key Responsibilities: Independently execute block/IP-level analog layout from schematics, including area estimation, floorplan optimization, routing, a...

1. Head - VM - Exp (5 Yrs+ ) - Salary - 1 lakh - Noida Sec 90 2. Exec - VM - Exp (1-2 Yrs) - 30k - Noida - Sec 90 3. Mgr - VM - Exp ( 2-5 Yrs) - 65k - Noida - Sec 90 Cluster VM for south India Call Yash @ 8017011445 - yash.khanna.onesource@gmail.com

Will be technically driving team Custom Circuit IO and Datapath solutions for next generation Memory in advanced CMOS technology nodes. Will work on architecture of High speed IO and DataPath solutions to meet the specifications and product requirements Work closely with team and actively participate in technical discussions and reviews. Pro-actively get design issues/problems solved. Contribute to or propose innovative design solutions and design methodologies. Qualifications Bachelors/Masters degree in Electronics & Telecommunication/Electrical engineering Hand-on design knowledge on both analog & mixed signal design environment. 8+ years of Experienc

Will be technically driving team Custom Circuit IO and Datapath solutions for next generation Memory in advanced CMOS technology nodes. Will work on architecture of High speed IO and DataPath solutions to meet the specifications and product requirements Work closely with team and actively participate in technical discussions and reviews. Pro-actively get design issues/problems solved. Contribute to or propose innovative design solutions and design methodologies. Qualifications Bachelors/Masters degree in Electronics & Telecommunication/Electrical engineering Hand-on design knowledge on both analog & mixed signal design environment. 8+ years of Experienc

Actively contribute to provide Custom Datapath solutions for next generation Memory in advanced CMOS technology nodes. Designing Datapath (custom and/or RTL) Blocks, Full chip Timing Finesim Design closure to meet the specifications and product requirements Work closely with team and actively participate in technical discussions and reviews. Pro-actively get design issues/problems solved. Contribute to or propose innovative design solutions and design methodologies. Qualifications Bachelors/Masters degree in Electronics & Telecommunication/Electrical engineering (VLSI Design) Hands-on design knowledge on both Digital custom, Analog & mixed signal design environment. 4+ years of Experience on...

Position: Physical Design Engineer (IS100FF RM 3490) Responsibilities Required Experience: Lead Netlist to-GDSII implementation, including floorplanning, power planning, placement, CTS, routing, and full signoff (DRC, LVS, STA, EMIR). Own and drive PnR execution and closure at both block and top levels, addressing timing, congestion, IR-drop, and physical verification challenges. Proficient with industry-standard tools: Cadence Innovus, Synopsys ICC2, and scripting in Tcl, Perl, Python for automation and flow development. Deep expertise in low-power design (UPF/CPF), clock gating, logic optimization, and integration of high-speed interfaces like DDR and PCIe. Collaborate cross-functionally w...