FinFET Layout Engineer

5 - 10 years

5 - 15 Lacs

Posted:2 days ago| Platform: Naukri logo

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Job Type

Full Time

Job Description

FinFET Layout Engineer

We are seeking a highly motivated and experienced FinFET Layout Engineer to join our team. In this role, you will be responsible for the physical layout and verification of complex integrated circuits using deep nanometer FinFET technology. You will work closely with circuit designers to ensure optimal performance, manufacturability, and reliability of our products.

Key Responsibilities

  • Perform physical layout of analog, digital, and mixed-signal circuits using Cadence tools.
  • Work with deep nanometer FinFET technology nodes.
  • Collaborate with circuit designers to optimize layout for performance and area.
  • Perform Design Rule Checking (DRC) and Layout Versus Schematic (LVS) verification.
  • Identify and resolve layout-related issues.
  • Contribute to the development and improvement of layout methodologies.
  • Participate in tape-out activities.

Skills Required

  • Proficiency in Cadence layout tools (e.g., Virtuoso).
  • Strong understanding of FinFET technology and deep nanometer design rules.
  • Experience with DRC and LVS verification tools (e.g., Calibre).
  • Knowledge of layout techniques for analog, digital, and mixed-signal circuits.
  • Ability to work independently and as part of a team.
  • Excellent problem-solving skills.

Requirements

  • Bachelor's or Master's degree in Electrical Engineering or a related field.
  • Proven experience in physical layout of integrated circuits.
  • Experience with FinFET technology is essential.
  • Experience with deep nanometer technology nodes (e.g., 7nm, 5nm, 3nm).
  • Experience with Cadence tools and DRC/LVS verification.

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