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Posted:1 day ago| Platform: Naukri logo

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Hybrid

Job Type

Full Time

Job Description

• Should have worked hands-on extensively on full chip DFT design,
• implementation, vector generation/verification, JTAG, Boundary scan & Simulation. • Experience with Scan, Compression, ATPG & Simulations with Mentor/Synopsys/ Cadence tools.

Required Candidate profile

• Participated in Successful Tapeouts of SoC/ASIC chips at 14nm or below. • Develop/Automate flows & scripts in Perl/Tcl to enhance the DFT methodologies & process.• Logic BIST knowledge is a plus.

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