Design Verification Principal Engineer

About Marvell

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Your Team, Your Impact

Marvell Data Centre Engineering (DCE) - Compute & Storage (CCS) BU has been at the forefront of developing and delivering leading-edge, high-performance data processing silicon platforms. By delivering a stream of technical innovations through a diverse set of fast growing product lines, Marvell technology is powering the next generation data processing and workload acceleration platforms for the Carrier, Cloud/Enterprise and Automotive Compute market segments. The team focusses on the Custom ASIC business, Cloud AI solutions & Enterprise/Career solutions including the CXL product line.

What You Can Expect

Job Responsibilities: SOC, Sub system & Block verification activities - should have participated in successful completion of SOC/Subsys projects across all phases from SOC/Subsys Specification to Silicon. Responsible for complete SOC/Subsys/Block verification activities like - develop verification architecture and verification plan, develop UVM based testbench, Integrate in-house verification components + complex VIP s ( ARM, Cadence, Synopsys, etc), develop test cases (UVM & assembly), verify and do coverage analysis in RTL and gate level design. Conduct reviews in all the SOC/Subsys verification phases, to achieve desired quality + on-schedule deliverables and drive SOC/Subsys verification process improvement. Mentor junior engineers and technically guide and monitor them on their day to day technical tasks. Work effectively with a global team and be self-motivated to manage deliverables Communicate clearly both verbally and in writing.

What Were Looking For

Technical Requirement s: Bachelor s degree in CS/EE with 14 18 years of relevant experience, or Master degree in CS/EE with 12 16 years of relevant experience Must Lead a team of 4-6 engineers Experience in SOC/Subsys level/Block verification of ARM-based SOCs; experience in ARM based boot environment preferred. Knowledgeable of ARM architecture and AMBA bus standards like AXI-4, CHI and ACE. Experience with industry standard interfaces such as DDR, eMMC, PCIE, Ethernet and USB. Experience in coding UVM SOC/Subsys level testbenches, BFM, scoreboards, monitors, etc. Proficient in writing and debugging tests in UVM as well as C. Exposure to Cadence, Synopsys, Mentor and/or ARM verification tools. Experience with assertion-based formal verification tools. Proficient in programming in scripting languages such as tcl and Perl. Understanding of hardware emulation support. Familiarity with TLMs in SystemC. Experience in Version tools like CVS, SVN, GIT etc.

Additional Compensation and Benefit Elements

With competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We re dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it s like to work at Marvell, visit our Careers page.

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.

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