Design Verification Engineer

Capgemini

4 - 7 years

6 - 16 Lacs

bengaluru

Posted:1 week ago| Platform:

Apply

Skills Required

c/c++ verilog compiler simulator system verilog uvm python shell questa cadence perl embedded systems

Work Mode

Hybrid

Job Type

Full Time

Job Description

Design Verification Engineer

Key Responsibilities:

Perform
pre-silicon verification
for complex SoCs/IPs using simulation-based techniques.
Develop and execute
verification plans
,
test benches
, and
test cases
.
Write and debug
functional tests
and generate
directed/random stimulus
to uncover design bugs.
Analyze waveforms, debug failures, and provide
root cause analysis
.

Required Skills:

Strong expertise in
SystemVerilog
,
UVM
, and simulation tools (e.g.,
VCS
,
Cadence
,
Questa
).
Hands-on experience with
debug tools
and coverage-driven verification methodologies.
Proficiency in
C/C++
for embedded systems and test environments.
Good scripting skills in
Perl
,
Python
, or
Shell
for automation.
Solid understanding of
verification methodologies
and
coverage analysis
.

Nice to Have:

Experience in
complex SoC/IP verification
.
Familiarity with
embedded systems
and hardware/software co-verification.

More Jobs at Capgemini

Data Scientist (Python, GenAI)

Pune, Mumbai, Bengaluru

6 - 9 yrs

INR 12 - 16 Lacs

Blue Prism Rpa Developer

Chennai, Pune, Mumbai (All Areas)

3 - 8 yrs

INR 5 - 15 Lacs

Java + Automation Architect

Navi Mumbai

11 - 15 yrs

INR 15 - 22 Lacs

VMware Admin

Pune

6 - 10 yrs

INR 4 - 8 Lacs

PYSPARK DEVELOPER

Pune

4 - 9 yrs

INR 4 - 7 Lacs

Mock Interview

Practice Video Interview with JobPe AI

Start Python Interview

Start Your Job Search Today

Browse through a variety of job opportunities tailored to your skills and preferences. Filter by location, experience, salary, and more to find your perfect fit.