Design Verification Engineer

As an experienced Verification Engineer with a minimum of 5 years of experience, your primary responsibility will be to lead the verification of DDR memory controller and PHY designs in compliance with DDR standards like DDR3, DDR4, DDR5, and other memory interface protocols. You will be required to develop and implement scalable, reusable, and efficient verification environments and testbenches for DDR designs using SystemVerilog, UVM, and other industry-standard methodologies. Ensuring protocol compliance is crucial, which includes validating command, data, and clock synchronization, read/write cycles, burst transfers, refresh cycles, error handling, and power management. Your role will involve creating detailed verification plans based on DDR specifications and requirements, focusing on corner cases, timing, and protocol validation for full coverage. Running simulations, debugging issues using tools like Questa, VCS, or ModelSim, and applying advanced debugging techniques such as waveform analysis, assertion-based verification, and code coverage will be part of your daily tasks. You will set up and manage regression testing for DDR functionality to ensure continuous validation and early detection of design issues. Achieving high functional and protocol coverage is vital, ensuring that timing constraints, corner cases, and failure scenarios are thoroughly verified. Implementing formal verification techniques to validate critical components of the DDR design, ensuring correctness in timing and data flow, and verifying crucial operations will also be part of your responsibilities. This position requires a Bachelor's or Master's degree in ECE/EEE or VLSI/Electronics from a reputable institution. The position is based in Bangalore/Hyderabad.,