Design Verification Engineer ACL Digital

8.0 - 10.0 years

0 Lacs

bengaluru, karnataka, india

On-site

ACL Digital Hiring for the below requirement Designation: DV engineers Experience: 8-10+ years Location: Bangalore Job Description: 1. Hands-on experiences on SV/UVM/Specman 2. Familiarity with formal-based verification 3. Running regression and debugging failures independently 4. Experience in functional and code coverages 5. Independently handling sub-module-level verification 6. Clear written/verbal communication skills. 7. Familiarity with PIPE i/f or Ethernet is a must; it's good to have basic knowledge of PCIe and/or high-speed Ethernet. 8. Familiarity in mixed signal IP (SerDes, DDR) verification will be a plus.

Posted 1 month ago

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Design Verification Engineer Sevya Multimedia

3.0 - 5.0 years

0 Lacs

hyderabad, telangana, india

On-site

We need experienced engineers to verify an IP/full-chip using System Verilog/UVM. Expertise in PCIe/DDR verification is preferable at IP/chip level. Skills: Overall 3+ years industry experience in Design Verification using System-Verilog/C/UVM. Generic knowhow on Digital Design and Verification methodologies. Experience in System Verilog/UVM based IP/SoC verification using advanced technologies. Good understanding of Constraint based Random verification; VIP coding; Test Plan design; Test cases coding; Coverage strategies and measurement Proficient in EDA tools used for Design Verification (e.g. Cadence/Mentor/Synopsys simulation suites; Verilator). Working knowledge of Unix, Linux and SKILL...

Posted 1 month ago

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Design Verification Engineer ACL Digital

5.0 - 9.0 years

0 Lacs

karnataka

On-site

As an experienced Verification Engineer with a minimum of 5 years of experience, your primary responsibility will be to lead the verification of DDR memory controller and PHY designs in compliance with DDR standards like DDR3, DDR4, DDR5, and other memory interface protocols. You will be required to develop and implement scalable, reusable, and efficient verification environments and testbenches for DDR designs using SystemVerilog, UVM, and other industry-standard methodologies. Ensuring protocol compliance is crucial, which includes validating command, data, and clock synchronization, read/write cycles, burst transfers, refresh cycles, error handling, and power management. Your role will in...

Posted 3 months ago

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