Design Lead

About Tessolve

Tessolve is a leading engineering solutions provider, enabling silicon and system companies to accelerate their products to market. With capabilities across silicon design, test engineering, and embedded solutions, we are an end-to-end partner for semiconductor companies globally.

Senior STA Engineer

Key Responsibilities

• Primetime

• Develop and validate timing constraints (SDC) for functional and DFT modes.

• Drive timing closure in collaboration with physical design, synthesis, and DFT teams.

• Analyze and resolve setup/hold, transition time, and cross-corner violations.

• Perform timing ECOs and timing model generation for hierarchical designs.

• OCV, AOCV, POCV

• TCL/Perl/Python

• Participate in customer calls and support project execution in a global delivery model.

Required Skills

• Strong fundamentals in STA, CMOS timing, and VLSI design concepts.

• Expertise in timing constraints, derating, and ECO implementation.

• Experience in hierarchical and flat STA at chip-level.

• Hands-on with timing sign-off methodologies across multiple PVT corners.

• Familiarity with clock domain crossing (CDC) and false path/multicycle path analysis.

• Working knowledge of physical design flows is a plus.

• Good communication and leadership skills.

Educational Qualifications

• B.E/B.Tech or M.E/M.Tech in Electronics or related discipline.

Nice to Have

• advanced technology nodes (5nm/3nm)

• low-power design techniques (UPF)

• Customer interaction and project leadership experience.