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Design For Test

5 - 9 years

0 Lacs

karnataka

Posted:2 days ago| Platform: Shine logo

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Skills Required

test methodologies socs dft jtag static timing analysis formal verification perl csh sh systemonchip designs memory bist scanatpg mentor synopsys dft tools verilog design unix scripting languages tcl

Work Mode

On-site

Job Type

Full Time

Job Description

You should have experience in designing and implementing test methodologies for large, complex SoCs. You must be capable of resolving scan issues in complex multi-clock domain designs, developing DFT strategies for complex System-On-Chip designs, and generating & integrating Memory BIST, JTAG, SCAN/ATPG. You should be an expert in analyzing fault coverage, delay fault, and enhancements. Experience in developing and running scan insertion scripts, performing ATPG simulation & analyzing results is required. Expertise in Mentor / Synopsys DFT tools and debug skills in a Verilog design environment is essential. Experience with static timing analysis (STA) & formal verification is desirable. Proficiency in common UNIX scripting languages (perl, tcl, csh, sh) is a must. Kindly email your resume to careers@perfectus.com with Job Code DFT in the subject line.,

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Design For Test

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Salary: Not disclosed

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