5.0 - 9.0 years

0 Lacs

karnataka

On-site

You should have experience in designing and implementing test methodologies for large, complex SoCs. You must be capable of resolving scan issues in complex multi-clock domain designs, developing DFT strategies for complex System-On-Chip designs, and generating & integrating Memory BIST, JTAG, SCAN/ATPG. You should be an expert in analyzing fault coverage, delay fault, and enhancements. Experience in developing and running scan insertion scripts, performing ATPG simulation & analyzing results is required. Expertise in Mentor / Synopsys DFT tools and debug skills in a Verilog design environment is essential. Experience with static timing analysis (STA) & formal verification is desirable. Proficiency in common UNIX scripting languages (perl, tcl, csh, sh) is a must. Kindly email your resume to careers@perfectus.com with Job Code DFT in the subject line.,

Posted 3 days ago

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