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ACL Digital
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Asic Rtl Design Engineer

Asic Rtl Design Engineer

ACL Digital

4 - 9 years

9 - 19 Lacs

bengaluru

Posted:6 hours ago| Platform:

Apply

Skills Required

lint cdc ascent synthesis real intent sta meridian rdc soc merdian timing constraints

Work Mode

Hybrid

Job Type

Full Time

Job Description

Hiring: SoC Design Implementation Engineer | Bangalore

4 30 Years

SoC Design Implementation Engineers

Key Responsibilities

Drive
Clock Domain Crossing (CDC)
and
Reset Domain Crossing (RDC)
analysis for complex SoCs.
Perform debug and
root-cause analysis
of CDC/RDC issues in collaboration with RTL and DV teams.
Own
RTL synthesis, constraint development (SDC), and optimization
for area, power, and timing.
Collaborate with
Physical Design (PD)
teams to ensure smooth RTL-to-GDS handoff.
Support
DFT integration
and readiness.
Contribute to design reviews, logical integrity checks, and signoff-quality handoff.

Technical Skills

Strong understanding of
RTL-to-GDSII flow
(synthesis, timing closure, CDC/RDC).
Hands-on experience with
Real Intent & Meridian tools
(very important).
Proficiency in CDC/RDC tools like
SpyGlass, Conformal CDC, VC CDC
.
Synthesis expertise with
Design Compiler, Genus
, or
Innovus
.
Solid knowledge of
SDC constraints, clock structures, MV/MC analysis
.
Experience with
formal linting, LEC, power-aware design flows
.
Good scripting skills (
TCL, Python, Shell
) for automation.
Exposure to
DFT flows and scan integration
(nice to have).

Soft Skills & Traits

Strong problem-solving & analytical mindset.
Excellent collaboration with RTL, PD, DV, and DFT teams.
Clear communicator with structured, checklist-driven approach.

Qualifications

B.E./B.Tech or M.E./M.Tech
in Electronics/Electrical or related field.
4 – 30 Years
of experience in SoC implementation, synthesis, and CDC/RDC verification.
Prior work on complex, multi-clock SoCs across advanced technology nodes preferred.

Apply Now

highly preferred

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