ASIC Physical Design, Staff Engineer

Job Description

Implementing and power signoff of world-class DDRs at cutting-edge technology nodes. Achieving timing closure above ~2GHz and integrating mixed signal macro IPs. Building efficient clock trees with very tight skew balancing. Providing regular updates to your manager on project status. Guiding junior peers with aspects of their job and contributing to their development. Representing the organization on business unit and/or company-wide projects. The Impact You Will Have: Driving the implementation of cutting-edge DDR technology, contributing to the advancement of high-performance computing. Ensuring the power efficiency and performance of our silicon chips, crucial for our competitive edge. Enhancing the reliability and integration of mixed signal macro IPs. Contributing to the overall success and innovation of Synopsys IP solutions. Mentoring junior engineers, fostering a culture of continuous learning and improvement. Representing Synopsys in key projects, influencing the direction and success of our initiatives. What You ll Need: Minimum of 5+ years of related experience in ASIC Physical Design. Proficiency in tools like DC, ICC2, StarRC, and PT-SI. Strong understanding of timing closure, power signoff, and mixed signal macro IP integration. Experience with DDR power signoff and clock tree building. Excellent problem-solving and analytical skills. Who You Are: A strong team player with excellent communication skills. Independent and collaborative, capable of working with minimal supervision. Creative and innovative, able to develop unique solutions to complex problems. Detail-oriented and organized, ensuring high-quality project outcomes. Passionate about continuous learning and professional growth.